Re: [RFC PATCH 3/3] target/mips: Make the number of TLB entries a CPU property

[Jiaxun Yang]

在 2020/10/13 21:25, Philippe Mathieu-Daudé 写道:
> Allow changing the number of TLB entries for
> testing/tunning purpose.
>
> Example to force a 34Kf cpu with 64 TLB:
>
>    $ qemu-system-mipsel -cpu 34Kf,tlb-entries=64 ...
>
> This is helpful for developers of the Yocto Project [*]:
>
>    Yocto Project uses qemu-system-mips 34Kf cpu model, to run 32bit
>    MIPS CI loop. It was observed that in this case CI test execution
>    time was almost twice longer than 64bit MIPS variant that runs
>    under MIPS64R2-generic model. It was investigated and concluded
>    that the difference in number of TLBs 16 in 34Kf case vs 64 in
>    MIPS64R2-generic is responsible for most of CI real time execution
>    difference. Because with 16 TLBs linux user-land trashes TLB more
>    and it needs to execute more instructions in TLB refill handler
>    calls, as result it runs much longer.
>
> [*] https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html
>
> Buglink: https://bugzilla.yoctoproject.org/show_bug.cgi?id=13992
> Reported-by: Victor Kamensky <kamensky@cisco.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
Hi Philippe,

I think name can this property vtlb-entries?

MIPS R2 had introduced dual-TLB feature and the entries specified here
is the number of VTLB, while FTLB is another set of entries with fixed 
pagesize.

Although MIPS TCG haven't implemented dual-TLB but it can prevent future
confusion.

Thanks.

- Jiaxun