Re: [RFC PATCH 0/3] target/mips: Make the number of TLB entries a CPU property

[Victor Kamensky (kamensky)]

Hi Philippe,

Thank you very much for looking at this. I gave a spin to
your 3 patch series in original setup, and as expected with
'-cpu 34Kf,tlb-entries=64' option it works great.

If nobody objects, and your patches could be merged, we
would greatly appreciate it.

Thanks,
Victor

________________________________________
From: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> on behalf of 
Philippe Mathieu-Daudé <f4bug@amsat.org>
Sent: Tuesday, October 13, 2020 6:25 AM
To: qemu-devel@nongnu.org; Victor Kamensky (kamensky)
Cc: Khem Raj; Richard Henderson; Aleksandar Rikalo; Aleksandar Markovic; Jiaxun 
Yang; Aurelien Jarno; Richard Purdie; Philippe Mathieu-Daudé
Subject: [RFC PATCH 0/3] target/mips: Make the number of TLB entries a CPU 
property

Yocto developers have expressed interest in running MIPS32

CPU with custom number of TLB:

https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html



Help them by making the number of TLB entries a CPU property,

keeping our set of CPU definitions in sync with real hardware.



Please test/review,



Phil.



Philippe Mathieu-Daudé (3):

  target/mips: Make cpu_mips_realize_env() propagate Error

  target/mips: Store number of TLB entries in CPUMIPSState

  target/mips: Make the number of TLB entries a CPU property



 target/mips/cpu.h                |  1 +

 target/mips/internal.h           | 10 +++++++++-

 target/mips/cpu.c                | 12 ++++++++++--

 target/mips/translate.c          | 16 ++++++++++++++--

 target/mips/translate_init.c.inc |  2 +-

 5 files changed, 35 insertions(+), 6 deletions(-)



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2.26.2