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[PULL 20/35] target/arm: Split out gen_gvec_fn_zz
From: |
Peter Maydell |
Subject: |
[PULL 20/35] target/arm: Split out gen_gvec_fn_zz |
Date: |
Fri, 28 Aug 2020 10:23:58 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Model the new function on gen_gvec_fn2 in translate-a64.c, but
indicating which kind of register and in which order. Since there
is only one user of do_vector2_z, fold it into do_mov_z.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200815013145.539409-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-sve.c | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index d97cb37d83f..f1803eb72bf 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -143,15 +143,13 @@ static int pred_gvec_reg_size(DisasContext *s)
}
/* Invoke a vector expander on two Zregs. */
-static bool do_vector2_z(DisasContext *s, GVecGen2Fn *gvec_fn,
- int esz, int rd, int rn)
+
+static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn *gvec_fn,
+ int esz, int rd, int rn)
{
- if (sve_access_check(s)) {
- unsigned vsz = vec_full_reg_size(s);
- gvec_fn(esz, vec_full_reg_offset(s, rd),
- vec_full_reg_offset(s, rn), vsz, vsz);
- }
- return true;
+ unsigned vsz = vec_full_reg_size(s);
+ gvec_fn(esz, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn), vsz, vsz);
}
/* Invoke a vector expander on three Zregs. */
@@ -170,7 +168,10 @@ static bool do_vector3_z(DisasContext *s, GVecGen3Fn
*gvec_fn,
/* Invoke a vector move on two Zregs. */
static bool do_mov_z(DisasContext *s, int rd, int rn)
{
- return do_vector2_z(s, tcg_gen_gvec_mov, 0, rd, rn);
+ if (sve_access_check(s)) {
+ gen_gvec_fn_zz(s, tcg_gen_gvec_mov, MO_8, rd, rn);
+ }
+ return true;
}
/* Initialize a Zreg with replications of a 64-bit immediate. */
--
2.20.1
- [PULL 13/35] hw/qdev-clock: Uninline qdev_connect_clock_in(), (continued)
- [PULL 13/35] hw/qdev-clock: Uninline qdev_connect_clock_in(), Peter Maydell, 2020/08/28
- [PULL 12/35] hw/arm/xilinx_zynq: Call qdev_connect_clock_in() before DeviceRealize, Peter Maydell, 2020/08/28
- [PULL 14/35] hw/qdev-clock: Avoid calling qdev_connect_clock_in after DeviceRealize, Peter Maydell, 2020/08/28
- [PULL 16/35] hw/misc/unimp: Display the value with width of the access size, Peter Maydell, 2020/08/28
- [PULL 15/35] hw/misc/unimp: Display value after offset, Peter Maydell, 2020/08/28
- [PULL 17/35] hw/misc/unimp: Display the offset with width of the region size, Peter Maydell, 2020/08/28
- [PULL 18/35] armsse: Define ARMSSEClass correctly, Peter Maydell, 2020/08/28
- [PULL 19/35] qemu/int128: Add int128_lshift, Peter Maydell, 2020/08/28
- [PULL 21/35] target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn, Peter Maydell, 2020/08/28
- [PULL 22/35] target/arm: Rearrange {sve,fp}_check_access assert, Peter Maydell, 2020/08/28
- [PULL 20/35] target/arm: Split out gen_gvec_fn_zz,
Peter Maydell <=
- [PULL 23/35] target/arm: Merge do_vector2_p into do_mov_p, Peter Maydell, 2020/08/28
- [PULL 24/35] target/arm: Clean up 4-operand predicate expansion, Peter Maydell, 2020/08/28
- [PULL 26/35] target/arm: Split out gen_gvec_ool_zzzp, Peter Maydell, 2020/08/28
- [PULL 25/35] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp, Peter Maydell, 2020/08/28
- [PULL 28/35] target/arm: Split out gen_gvec_ool_zzp, Peter Maydell, 2020/08/28
- [PULL 27/35] target/arm: Merge helper_sve_clr_* and helper_sve_movz_*, Peter Maydell, 2020/08/28
- [PULL 29/35] target/arm: Split out gen_gvec_ool_zzz, Peter Maydell, 2020/08/28
- [PULL 30/35] target/arm: Split out gen_gvec_ool_zz, Peter Maydell, 2020/08/28
- [PULL 32/35] target/arm: Generalize inl_qrdmlah_* helper functions, Peter Maydell, 2020/08/28
- [PULL 31/35] target/arm: Tidy SVE tszimm shift formats, Peter Maydell, 2020/08/28