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[PULL 19/35] qemu/int128: Add int128_lshift
From: |
Peter Maydell |
Subject: |
[PULL 19/35] qemu/int128: Add int128_lshift |
Date: |
Fri, 28 Aug 2020 10:23:57 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Add left-shift to match the existing right-shift.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200815013145.539409-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/qemu/int128.h | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/include/qemu/int128.h b/include/qemu/int128.h
index 5c9890db8b3..76ea405922d 100644
--- a/include/qemu/int128.h
+++ b/include/qemu/int128.h
@@ -63,6 +63,11 @@ static inline Int128 int128_rshift(Int128 a, int n)
return a >> n;
}
+static inline Int128 int128_lshift(Int128 a, int n)
+{
+ return a << n;
+}
+
static inline Int128 int128_add(Int128 a, Int128 b)
{
return a + b;
@@ -217,6 +222,17 @@ static inline Int128 int128_rshift(Int128 a, int n)
}
}
+static inline Int128 int128_lshift(Int128 a, int n)
+{
+ uint64_t l = a.lo << (n & 63);
+ if (n >= 64) {
+ return int128_make128(0, l);
+ } else if (n > 0) {
+ return int128_make128(l, (a.hi << n) | (a.lo >> (64 - n)));
+ }
+ return a;
+}
+
static inline Int128 int128_add(Int128 a, Int128 b)
{
uint64_t lo = a.lo + b.lo;
--
2.20.1
- [PULL 09/35] hw/sd/allwinner-sdhost: Use AddressSpace for DMA transfers, (continued)
- [PULL 09/35] hw/sd/allwinner-sdhost: Use AddressSpace for DMA transfers, Peter Maydell, 2020/08/28
- [PULL 10/35] hw/net/allwinner-sun8i-emac: Use AddressSpace for DMA transfers, Peter Maydell, 2020/08/28
- [PULL 11/35] hw/arm/xilinx_zynq: Uninline cadence_uart_create(), Peter Maydell, 2020/08/28
- [PULL 13/35] hw/qdev-clock: Uninline qdev_connect_clock_in(), Peter Maydell, 2020/08/28
- [PULL 12/35] hw/arm/xilinx_zynq: Call qdev_connect_clock_in() before DeviceRealize, Peter Maydell, 2020/08/28
- [PULL 14/35] hw/qdev-clock: Avoid calling qdev_connect_clock_in after DeviceRealize, Peter Maydell, 2020/08/28
- [PULL 16/35] hw/misc/unimp: Display the value with width of the access size, Peter Maydell, 2020/08/28
- [PULL 15/35] hw/misc/unimp: Display value after offset, Peter Maydell, 2020/08/28
- [PULL 17/35] hw/misc/unimp: Display the offset with width of the region size, Peter Maydell, 2020/08/28
- [PULL 18/35] armsse: Define ARMSSEClass correctly, Peter Maydell, 2020/08/28
- [PULL 19/35] qemu/int128: Add int128_lshift,
Peter Maydell <=
- [PULL 21/35] target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn, Peter Maydell, 2020/08/28
- [PULL 22/35] target/arm: Rearrange {sve,fp}_check_access assert, Peter Maydell, 2020/08/28
- [PULL 20/35] target/arm: Split out gen_gvec_fn_zz, Peter Maydell, 2020/08/28
- [PULL 23/35] target/arm: Merge do_vector2_p into do_mov_p, Peter Maydell, 2020/08/28
- [PULL 24/35] target/arm: Clean up 4-operand predicate expansion, Peter Maydell, 2020/08/28
- [PULL 26/35] target/arm: Split out gen_gvec_ool_zzzp, Peter Maydell, 2020/08/28
- [PULL 25/35] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp, Peter Maydell, 2020/08/28
- [PULL 28/35] target/arm: Split out gen_gvec_ool_zzp, Peter Maydell, 2020/08/28
- [PULL 27/35] target/arm: Merge helper_sve_clr_* and helper_sve_movz_*, Peter Maydell, 2020/08/28
- [PULL 29/35] target/arm: Split out gen_gvec_ool_zzz, Peter Maydell, 2020/08/28