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[PULL 22/27] target/arm/translate.c: Delete/amend incorrect comments
From: |
Peter Maydell |
Subject: |
[PULL 22/27] target/arm/translate.c: Delete/amend incorrect comments |
Date: |
Mon, 24 Aug 2020 10:48:06 +0100 |
In arm_tr_init_disas_context() we have a FIXME comment that suggests
"cpu_M0 can probably be the same as cpu_V0". This isn't in fact
possible: cpu_V0 is used as a temporary inside gen_iwmmxt_shift(),
and that function is called in various places where cpu_M0 contains a
live value (i.e. between gen_op_iwmmxt_movq_M0_wRn() and
gen_op_iwmmxt_movq_wRn_M0() calls). Remove the comment.
We also have a comment on the declarations of cpu_V0/V1/M0 which
claims they're "for efficiency". This isn't true with modern TCG, so
replace this comment with one which notes that they're only used with
the iwmmxt decode.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200803132815.3861-1-peter.maydell@linaro.org
---
target/arm/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 4ffd8b1fbe5..dd25adcf402 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -57,8 +57,9 @@
#define IS_USER(s) (s->user)
#endif
-/* We reuse the same 64-bit temporaries for efficiency. */
+/* These are TCG temporaries used only by the legacy iwMMXt decoder */
static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
+/* These are TCG globals which alias CPUARMState fields */
static TCGv_i32 cpu_R[16];
TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF;
TCGv_i64 cpu_exclusive_addr;
@@ -8566,7 +8567,6 @@ static void arm_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
cpu_V0 = tcg_temp_new_i64();
cpu_V1 = tcg_temp_new_i64();
- /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
cpu_M0 = tcg_temp_new_i64();
}
--
2.20.1
- [PULL 12/27] hw/arm/smmuv3: Advertise SMMUv3.2 range invalidation, (continued)
- [PULL 12/27] hw/arm/smmuv3: Advertise SMMUv3.2 range invalidation, Peter Maydell, 2020/08/24
- [PULL 13/27] docs/system/arm: Document the Xilinx Versal Virt board, Peter Maydell, 2020/08/24
- [PULL 14/27] target/arm: Pull handling of XScale insns out of disas_coproc_insn(), Peter Maydell, 2020/08/24
- [PULL 15/27] target/arm: Separate decode from handling of coproc insns, Peter Maydell, 2020/08/24
- [PULL 16/27] target/arm: Convert A32 coprocessor insns to decodetree, Peter Maydell, 2020/08/24
- [PULL 17/27] target/arm: Tidy up disas_arm_insn(), Peter Maydell, 2020/08/24
- [PULL 18/27] target/arm: Do M-profile NOCP checks early and via decodetree, Peter Maydell, 2020/08/24
- [PULL 20/27] target/arm: Remove ARCH macro, Peter Maydell, 2020/08/24
- [PULL 19/27] target/arm: Convert T32 coprocessor insns to decodetree, Peter Maydell, 2020/08/24
- [PULL 21/27] target/arm: Delete unused VFP_DREG macros, Peter Maydell, 2020/08/24
- [PULL 22/27] target/arm/translate.c: Delete/amend incorrect comments,
Peter Maydell <=
- [PULL 23/27] target/arm: Delete unused ARM_FEATURE_CRC, Peter Maydell, 2020/08/24
- [PULL 25/27] target/arm: Make A32/T32 use new fpstatus_ptr() API, Peter Maydell, 2020/08/24
- [PULL 24/27] target/arm: Replace A64 get_fpstatus_ptr() with generic fpstatus_ptr(), Peter Maydell, 2020/08/24
- [PULL 27/27] target/arm: Use correct FPST for VCMLA, VCADD on fp16, Peter Maydell, 2020/08/24
- [PULL 26/27] target/arm: Implement FPST_STD_F16 fpstatus, Peter Maydell, 2020/08/24
- Re: [PULL 00/27] target-arm queue, Peter Maydell, 2020/08/24