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[PULL 11/27] hw/arm/smmuv3: Support HAD and advertise SMMUv3.1 support
From: |
Peter Maydell |
Subject: |
[PULL 11/27] hw/arm/smmuv3: Support HAD and advertise SMMUv3.1 support |
Date: |
Mon, 24 Aug 2020 10:47:55 +0100 |
From: Eric Auger <eric.auger@redhat.com>
HAD is a mandatory features with SMMUv3.1 if S1P is set, which is
our case. Other 3.1 mandatory features come with S2P which we don't
have.
So let's support HAD and advertise SMMUv3.1 support in AIDR.
HAD support allows the CD to disable hierarchical attributes, ie.
if the HAD0/1 bit is set, the APTable field of table descriptors
walked through TTB0/1 is ignored.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-11-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/smmuv3-internal.h | 2 ++
include/hw/arm/smmu-common.h | 1 +
hw/arm/smmu-common.c | 2 +-
hw/arm/smmuv3.c | 6 +++++-
hw/arm/trace-events | 2 +-
5 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index bd34a4f3300..9ae7d97fafd 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -54,6 +54,7 @@ REG32(IDR1, 0x4)
REG32(IDR2, 0x8)
REG32(IDR3, 0xc)
+ FIELD(IDR3, HAD, 2, 1);
REG32(IDR4, 0x10)
REG32(IDR5, 0x14)
FIELD(IDR5, OAS, 0, 3);
@@ -578,6 +579,7 @@ static inline int pa_range(STE *ste)
lo = (x)->word[(sel) * 2 + 2] & ~0xfULL; \
hi | lo; \
})
+#define CD_HAD(x, sel) extract32((x)->word[(sel) * 2 + 2], 1, 1)
#define CD_TSZ(x, sel) extract32((x)->word[0], (16 * (sel)) + 0, 6)
#define CD_TG(x, sel) extract32((x)->word[0], (16 * (sel)) + 6, 2)
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
index 4f6acf634cf..880dccd7c04 100644
--- a/include/hw/arm/smmu-common.h
+++ b/include/hw/arm/smmu-common.h
@@ -50,6 +50,7 @@ typedef struct SMMUTransTableInfo {
uint64_t ttb; /* TT base address */
uint8_t tsz; /* input range, ie. 2^(64 -tsz)*/
uint8_t granule_sz; /* granule page shift */
+ bool had; /* hierarchical attribute disable */
} SMMUTransTableInfo;
typedef struct SMMUTLBEntry {
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index 8d89a86699a..3838db13952 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -316,7 +316,7 @@ static int smmu_ptw_64(SMMUTransCfg *cfg,
if (is_table_pte(pte, level)) {
ap = PTE_APTABLE(pte);
- if (is_permission_fault(ap, perm)) {
+ if (is_permission_fault(ap, perm) && !tt->had) {
info->type = SMMU_PTW_ERR_PERMISSION;
goto error;
}
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 718f28462ea..b262f0e4a74 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -254,6 +254,8 @@ static void smmuv3_init_regs(SMMUv3State *s)
s->idr[1] = FIELD_DP32(s->idr[1], IDR1, EVENTQS, SMMU_EVENTQS);
s->idr[1] = FIELD_DP32(s->idr[1], IDR1, CMDQS, SMMU_CMDQS);
+ s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1);
+
/* 4K and 64K granule support */
s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1);
s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1);
@@ -270,6 +272,7 @@ static void smmuv3_init_regs(SMMUv3State *s)
s->features = 0;
s->sid_split = 0;
+ s->aidr = 0x1;
}
static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
@@ -506,7 +509,8 @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd,
SMMUEventInfo *event)
if (tt->ttb & ~(MAKE_64BIT_MASK(0, cfg->oas))) {
goto bad_cd;
}
- trace_smmuv3_decode_cd_tt(i, tt->tsz, tt->ttb, tt->granule_sz);
+ tt->had = CD_HAD(cd, i);
+ trace_smmuv3_decode_cd_tt(i, tt->tsz, tt->ttb, tt->granule_sz,
tt->had);
}
event->record_trans_faults = CD_R(cd);
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
index 3d905e0f7d0..c8a4d80f6bd 100644
--- a/hw/arm/trace-events
+++ b/hw/arm/trace-events
@@ -39,7 +39,7 @@ smmuv3_translate_abort(const char *n, uint16_t sid, uint64_t
addr, bool is_write
smmuv3_translate_success(const char *n, uint16_t sid, uint64_t iova, uint64_t
translated, int perm) "%s sid=%d iova=0x%"PRIx64" translated=0x%"PRIx64"
perm=0x%x"
smmuv3_get_cd(uint64_t addr) "CD addr: 0x%"PRIx64
smmuv3_decode_cd(uint32_t oas) "oas=%d"
-smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz)
"TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d"
+smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz,
bool had) "TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d had:%d"
smmuv3_cmdq_cfgi_ste(int streamid) "streamid =%d"
smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%d - end=0x%d"
smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid = %d"
--
2.20.1
- [PULL 01/27] hw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores, (continued)
- [PULL 01/27] hw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores, Peter Maydell, 2020/08/24
- [PULL 02/27] hw/arm/smmu-common: Factorize some code in smmu_ptw_64(), Peter Maydell, 2020/08/24
- [PULL 04/27] hw/arm/smmu: Introduce smmu_get_iotlb_key(), Peter Maydell, 2020/08/24
- [PULL 03/27] hw/arm/smmu-common: Add IOTLB helpers, Peter Maydell, 2020/08/24
- [PULL 05/27] hw/arm/smmu: Introduce SMMUTLBEntry for PTW and IOTLB value, Peter Maydell, 2020/08/24
- [PULL 06/27] hw/arm/smmu-common: Manage IOTLB block entries, Peter Maydell, 2020/08/24
- [PULL 07/27] hw/arm/smmuv3: Introduce smmuv3_s1_range_inval() helper, Peter Maydell, 2020/08/24
- [PULL 08/27] hw/arm/smmuv3: Get prepared for range invalidation, Peter Maydell, 2020/08/24
- [PULL 09/27] hw/arm/smmuv3: Fix IIDR offset, Peter Maydell, 2020/08/24
- [PULL 10/27] hw/arm/smmuv3: Let AIDR advertise SMMUv3.0 support, Peter Maydell, 2020/08/24
- [PULL 11/27] hw/arm/smmuv3: Support HAD and advertise SMMUv3.1 support,
Peter Maydell <=
- [PULL 12/27] hw/arm/smmuv3: Advertise SMMUv3.2 range invalidation, Peter Maydell, 2020/08/24
- [PULL 13/27] docs/system/arm: Document the Xilinx Versal Virt board, Peter Maydell, 2020/08/24
- [PULL 14/27] target/arm: Pull handling of XScale insns out of disas_coproc_insn(), Peter Maydell, 2020/08/24
- [PULL 15/27] target/arm: Separate decode from handling of coproc insns, Peter Maydell, 2020/08/24
- [PULL 16/27] target/arm: Convert A32 coprocessor insns to decodetree, Peter Maydell, 2020/08/24
- [PULL 17/27] target/arm: Tidy up disas_arm_insn(), Peter Maydell, 2020/08/24
- [PULL 18/27] target/arm: Do M-profile NOCP checks early and via decodetree, Peter Maydell, 2020/08/24
- [PULL 20/27] target/arm: Remove ARCH macro, Peter Maydell, 2020/08/24
- [PULL 19/27] target/arm: Convert T32 coprocessor insns to decodetree, Peter Maydell, 2020/08/24
- [PULL 21/27] target/arm: Delete unused VFP_DREG macros, Peter Maydell, 2020/08/24