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[PULL 10/27] hw/arm/smmuv3: Let AIDR advertise SMMUv3.0 support
From: |
Peter Maydell |
Subject: |
[PULL 10/27] hw/arm/smmuv3: Let AIDR advertise SMMUv3.0 support |
Date: |
Mon, 24 Aug 2020 10:47:54 +0100 |
From: Eric Auger <eric.auger@redhat.com>
Add the support for AIDR register. It currently advertises
SMMU V3.0 spec.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-10-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/smmuv3-internal.h | 1 +
include/hw/arm/smmuv3.h | 1 +
hw/arm/smmuv3.c | 3 +++
3 files changed, 5 insertions(+)
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index ef093eaff50..bd34a4f3300 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -64,6 +64,7 @@ REG32(IDR5, 0x14)
#define SMMU_IDR5_OAS 4
REG32(IIDR, 0x18)
+REG32(AIDR, 0x1c)
REG32(CR0, 0x20)
FIELD(CR0, SMMU_ENABLE, 0, 1)
FIELD(CR0, EVENTQEN, 2, 1)
diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
index 36b2f452539..68d7a963e0f 100644
--- a/include/hw/arm/smmuv3.h
+++ b/include/hw/arm/smmuv3.h
@@ -41,6 +41,7 @@ typedef struct SMMUv3State {
uint32_t idr[6];
uint32_t iidr;
+ uint32_t aidr;
uint32_t cr[3];
uint32_t cr0ack;
uint32_t statusr;
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 89ab11fc36a..718f28462ea 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -1251,6 +1251,9 @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr
offset,
case A_IIDR:
*data = s->iidr;
return MEMTX_OK;
+ case A_AIDR:
+ *data = s->aidr;
+ return MEMTX_OK;
case A_CR0:
*data = s->cr[0];
return MEMTX_OK;
--
2.20.1
- [PULL 00/27] target-arm queue, Peter Maydell, 2020/08/24
- [PULL 01/27] hw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores, Peter Maydell, 2020/08/24
- [PULL 02/27] hw/arm/smmu-common: Factorize some code in smmu_ptw_64(), Peter Maydell, 2020/08/24
- [PULL 04/27] hw/arm/smmu: Introduce smmu_get_iotlb_key(), Peter Maydell, 2020/08/24
- [PULL 03/27] hw/arm/smmu-common: Add IOTLB helpers, Peter Maydell, 2020/08/24
- [PULL 05/27] hw/arm/smmu: Introduce SMMUTLBEntry for PTW and IOTLB value, Peter Maydell, 2020/08/24
- [PULL 06/27] hw/arm/smmu-common: Manage IOTLB block entries, Peter Maydell, 2020/08/24
- [PULL 07/27] hw/arm/smmuv3: Introduce smmuv3_s1_range_inval() helper, Peter Maydell, 2020/08/24
- [PULL 08/27] hw/arm/smmuv3: Get prepared for range invalidation, Peter Maydell, 2020/08/24
- [PULL 09/27] hw/arm/smmuv3: Fix IIDR offset, Peter Maydell, 2020/08/24
- [PULL 10/27] hw/arm/smmuv3: Let AIDR advertise SMMUv3.0 support,
Peter Maydell <=
- [PULL 11/27] hw/arm/smmuv3: Support HAD and advertise SMMUv3.1 support, Peter Maydell, 2020/08/24
- [PULL 12/27] hw/arm/smmuv3: Advertise SMMUv3.2 range invalidation, Peter Maydell, 2020/08/24
- [PULL 13/27] docs/system/arm: Document the Xilinx Versal Virt board, Peter Maydell, 2020/08/24
- [PULL 14/27] target/arm: Pull handling of XScale insns out of disas_coproc_insn(), Peter Maydell, 2020/08/24
- [PULL 15/27] target/arm: Separate decode from handling of coproc insns, Peter Maydell, 2020/08/24
- [PULL 16/27] target/arm: Convert A32 coprocessor insns to decodetree, Peter Maydell, 2020/08/24
- [PULL 17/27] target/arm: Tidy up disas_arm_insn(), Peter Maydell, 2020/08/24
- [PULL 18/27] target/arm: Do M-profile NOCP checks early and via decodetree, Peter Maydell, 2020/08/24
- [PULL 20/27] target/arm: Remove ARCH macro, Peter Maydell, 2020/08/24
- [PULL 19/27] target/arm: Convert T32 coprocessor insns to decodetree, Peter Maydell, 2020/08/24