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Re: [RFC 01/65] target/riscv: fix rsub gvec tcg_assert_listed_vecop asse
From: |
Alistair Francis |
Subject: |
Re: [RFC 01/65] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion |
Date: |
Fri, 10 Jul 2020 11:24:50 -0700 |
On Fri, Jul 10, 2020 at 9:13 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> > From: Frank Chang <frank.chang@sifive.com>
> >
> > gvec should provide vecop_list to avoid:
> > "tcg_tcg_assert_listed_vecop: code should not be reached bug" assertion.
> >
> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
> > ---
> > target/riscv/insn_trans/trans_rvv.inc.c | 5 +++++
> > 1 file changed, 5 insertions(+)
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> Alistair, this one should be queued for 5.1 as a bug fix.
Thanks for reviewing these. I have applied the first 4 to my PR for 5.1.
Alistair
>
>
> r~
>
- [RFC 00/65] target/riscv: support vector extension v0.9, frank . chang, 2020/07/10
- [RFC 06/65] target/riscv: rvv-0.9: add vcsr register, frank . chang, 2020/07/10
- [RFC 01/65] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion, frank . chang, 2020/07/10
- [RFC 08/65] target/riscv: rvv-0.9: update mstatus_vs by tb_flags, frank . chang, 2020/07/10
- [RFC 12/65] target/riscv: rvv-0.9: update check functions, frank . chang, 2020/07/10
- [RFC 15/65] target/riscv: rvv-0.9: index load and store instructions, frank . chang, 2020/07/10
- [RFC 17/65] target/riscv: rvv-0.9: fault-only-first unit stride load, frank . chang, 2020/07/10
- [RFC 18/65] target/riscv: rvv-0.9: amo operations, frank . chang, 2020/07/10
- [RFC 02/65] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64(), frank . chang, 2020/07/10