[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [RFC 06/65] target/riscv: rvv-0.9: add vcsr register
From: |
Richard Henderson |
Subject: |
Re: [RFC 06/65] target/riscv: rvv-0.9: add vcsr register |
Date: |
Fri, 10 Jul 2020 10:02:28 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 |
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> + [CSR_VCSR] = { vs, read_vcsr, write_vcsr
> },
As long as you have the vext_spec argument, you need a separate vs_0_9
predicate function, so that this csr is not available to VEXT_VERSION_0_07_1.
r~
- [RFC 00/65] target/riscv: support vector extension v0.9, frank . chang, 2020/07/10
- [RFC 06/65] target/riscv: rvv-0.9: add vcsr register, frank . chang, 2020/07/10
- Re: [RFC 06/65] target/riscv: rvv-0.9: add vcsr register,
Richard Henderson <=
- [RFC 01/65] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion, frank . chang, 2020/07/10
- [RFC 08/65] target/riscv: rvv-0.9: update mstatus_vs by tb_flags, frank . chang, 2020/07/10
- [RFC 12/65] target/riscv: rvv-0.9: update check functions, frank . chang, 2020/07/10
- [RFC 15/65] target/riscv: rvv-0.9: index load and store instructions, frank . chang, 2020/07/10
- [RFC 17/65] target/riscv: rvv-0.9: fault-only-first unit stride load, frank . chang, 2020/07/10