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[PATCH v3 05/21] target/xtensa: support copying registers up to 64 bits
From: |
Max Filippov |
Subject: |
[PATCH v3 05/21] target/xtensa: support copying registers up to 64 bits wide |
Date: |
Wed, 8 Jul 2020 15:20:45 -0700 |
FLIX dependency breaking code assumes that all registers are 32 bit
wide. This may not always be correct.
Extract actual register width from the associated register file and use
it to create temporaries of correct width and generate correct data
movement instructions.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
target/xtensa/cpu.h | 1 +
target/xtensa/translate.c | 26 +++++++++++++++++++++-----
2 files changed, 22 insertions(+), 5 deletions(-)
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 0409aa6189cf..960f6573447f 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -359,6 +359,7 @@ typedef struct opcode_arg {
uint32_t raw_imm;
void *in;
void *out;
+ uint32_t num_bits;
} OpcodeArg;
typedef struct DisasContext DisasContext;
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 9838bf6b3ec5..bc01a720719d 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -943,10 +943,10 @@ static void disas_xtensa_insn(CPUXtensaState *env,
DisasContext *dc)
for (opnd = vopnd = 0; opnd < opnds; ++opnd) {
void **register_file = NULL;
+ xtensa_regfile rf;
if (xtensa_operand_is_register(isa, opc, opnd)) {
- xtensa_regfile rf = xtensa_operand_regfile(isa, opc, opnd);
-
+ rf = xtensa_operand_regfile(isa, opc, opnd);
register_file = dc->config->regfile[rf];
if (rf == dc->config->a_regfile) {
@@ -972,6 +972,9 @@ static void disas_xtensa_insn(CPUXtensaState *env,
DisasContext *dc)
if (register_file) {
arg[vopnd].in = register_file[v];
arg[vopnd].out = register_file[v];
+ arg[vopnd].num_bits = xtensa_regfile_num_bits(isa, rf);
+ } else {
+ arg[vopnd].num_bits = 32;
}
++vopnd;
}
@@ -1111,8 +1114,15 @@ static void disas_xtensa_insn(CPUXtensaState *env,
DisasContext *dc)
for (i = j = 0; i < n_arg_copy; ++i) {
if (i == 0 || arg_copy[i].resource != resource) {
resource = arg_copy[i].resource;
- temp = tcg_temp_local_new();
- tcg_gen_mov_i32(temp, arg_copy[i].arg->in);
+ if (arg_copy[i].arg->num_bits <= 32) {
+ temp = tcg_temp_local_new_i32();
+ tcg_gen_mov_i32(temp, arg_copy[i].arg->in);
+ } else if (arg_copy[i].arg->num_bits <= 64) {
+ temp = tcg_temp_local_new_i64();
+ tcg_gen_mov_i64(temp, arg_copy[i].arg->in);
+ } else {
+ g_assert_not_reached();
+ }
arg_copy[i].temp = temp;
if (i != j) {
@@ -1143,7 +1153,13 @@ static void disas_xtensa_insn(CPUXtensaState *env,
DisasContext *dc)
}
for (i = 0; i < n_arg_copy; ++i) {
- tcg_temp_free(arg_copy[i].temp);
+ if (arg_copy[i].arg->num_bits <= 32) {
+ tcg_temp_free_i32(arg_copy[i].temp);
+ } else if (arg_copy[i].arg->num_bits <= 64) {
+ tcg_temp_free_i64(arg_copy[i].temp);
+ } else {
+ g_assert_not_reached();
+ }
}
if (dc->base.is_jmp == DISAS_NEXT) {
--
2.20.1
- Re: [PATCH 00/21] target/xtensa: implement double precision FPU, (continued)
[PATCH 00/21] target/xtensa: implement double precision FPU, Max Filippov, 2020/07/08
- [PATCH v3 01/21] softfloat: make NO_SIGNALING_NANS runtime property, Max Filippov, 2020/07/08
- [PATCH v3 02/21] softfloat: pass float_status pointer to pickNaN, Max Filippov, 2020/07/08
- [PATCH v3 03/21] softfloat: add xtensa specialization for pickNaNMulAdd, Max Filippov, 2020/07/08
- [PATCH v3 04/21] target/xtensa: add geometry to xtensa_get_regfile_by_name, Max Filippov, 2020/07/08
- [PATCH v3 05/21] target/xtensa: support copying registers up to 64 bits wide,
Max Filippov <=
- [PATCH v3 06/21] target/xtensa: rename FPU2000 translators and helpers, Max Filippov, 2020/07/08
- [PATCH v3 07/21] target/xtensa: move FSR/FCR register accessors, Max Filippov, 2020/07/08
- [PATCH v3 08/21] target/xtensa: don't access BR regfile directly, Max Filippov, 2020/07/08
- [PATCH v3 10/21] target/xtensa: implement FPU division and square root, Max Filippov, 2020/07/08
- [PATCH v3 11/21] tests/tcg/xtensa: fix test execution on ISS, Max Filippov, 2020/07/08
- [PATCH v3 13/21] tests/tcg/xtensa: expand madd tests, Max Filippov, 2020/07/08
- [PATCH v3 12/21] tests/tcg/xtensa: update test_fp0_arith for DFPU, Max Filippov, 2020/07/08
- [PATCH v3 09/21] target/xtensa: add DFP option, registers and opcodes, Max Filippov, 2020/07/08
- [PATCH v3 14/21] tests/tcg/xtensa: update test_fp0_conv for DFPU, Max Filippov, 2020/07/08
- [PATCH v3 18/21] tests/tcg/xtensa: test double precision load/store, Max Filippov, 2020/07/08