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[PATCH v3 03/21] softfloat: add xtensa specialization for pickNaNMulAdd
From: |
Max Filippov |
Subject: |
[PATCH v3 03/21] softfloat: add xtensa specialization for pickNaNMulAdd |
Date: |
Wed, 8 Jul 2020 15:20:43 -0700 |
pickNaNMulAdd logic on Xtensa is to apply pickNaN to the inputs of the
expression (a * b) + c. However if default NaN is produces as a result
of (a * b) calculation it is not considered when c is NaN.
So with two pickNaN variants there must be two pickNaNMulAdd variants.
In addition the invalid flag is always set when (a * b) produces NaN.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: "Alex Bennée" <alex.bennee@linaro.org>
Cc: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
Changes v2->v3:
- handle infzero case in pickNaNMulAdd properly and reword commit
message
fpu/softfloat-specialize.inc.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/fpu/softfloat-specialize.inc.c b/fpu/softfloat-specialize.inc.c
index f519beca1b74..914deac46ecf 100644
--- a/fpu/softfloat-specialize.inc.c
+++ b/fpu/softfloat-specialize.inc.c
@@ -585,6 +585,32 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass
b_cls, FloatClass c_cls,
} else {
return 1;
}
+#elif defined(TARGET_XTENSA)
+ /*
+ * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
+ * an input NaN if we have one (ie c).
+ */
+ if (infzero) {
+ float_raise(float_flag_invalid, status);
+ return 2;
+ }
+ if (status->use_first_nan) {
+ if (is_nan(a_cls)) {
+ return 0;
+ } else if (is_nan(b_cls)) {
+ return 1;
+ } else {
+ return 2;
+ }
+ } else {
+ if (is_nan(c_cls)) {
+ return 2;
+ } else if (is_nan(b_cls)) {
+ return 1;
+ } else {
+ return 0;
+ }
+ }
#else
/* A default implementation: prefer a to b to c.
* This is unlikely to actually match any real implementation.
--
2.20.1
- Re: [PATCH 00/21] target/xtensa: implement double precision FPU, (continued)
[PATCH 00/21] target/xtensa: implement double precision FPU, Max Filippov, 2020/07/08
- [PATCH v3 01/21] softfloat: make NO_SIGNALING_NANS runtime property, Max Filippov, 2020/07/08
- [PATCH v3 02/21] softfloat: pass float_status pointer to pickNaN, Max Filippov, 2020/07/08
- [PATCH v3 03/21] softfloat: add xtensa specialization for pickNaNMulAdd,
Max Filippov <=
- [PATCH v3 04/21] target/xtensa: add geometry to xtensa_get_regfile_by_name, Max Filippov, 2020/07/08
- [PATCH v3 05/21] target/xtensa: support copying registers up to 64 bits wide, Max Filippov, 2020/07/08
- [PATCH v3 06/21] target/xtensa: rename FPU2000 translators and helpers, Max Filippov, 2020/07/08
- [PATCH v3 07/21] target/xtensa: move FSR/FCR register accessors, Max Filippov, 2020/07/08
- [PATCH v3 08/21] target/xtensa: don't access BR regfile directly, Max Filippov, 2020/07/08
- [PATCH v3 10/21] target/xtensa: implement FPU division and square root, Max Filippov, 2020/07/08
- [PATCH v3 11/21] tests/tcg/xtensa: fix test execution on ISS, Max Filippov, 2020/07/08
- [PATCH v3 13/21] tests/tcg/xtensa: expand madd tests, Max Filippov, 2020/07/08
- [PATCH v3 12/21] tests/tcg/xtensa: update test_fp0_arith for DFPU, Max Filippov, 2020/07/08