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From: | Alex Bennée |
Subject: | Re: [PATCH 00/21] target/xtensa: implement double precision FPU |
Date: | Tue, 07 Jul 2020 20:21:50 +0100 |
User-agent: | mu4e 1.5.4; emacs 28.0.50 |
Max Filippov <jcmvbkbc@gmail.com> writes: > On Tue, Jul 7, 2020 at 4:31 AM Alex Bennée <alex.bennee@linaro.org> wrote: >> I've only looked at the softfloat bits as I'm not familiar with xtensa > > Thanks for taking a look! > >> at all. However you can have a vague: >> >> Tested-by: Alex Bennée <alex.bennee@linaro.org> >> >> for the series - congratulations you pass your own tests ;-) > > Unless you've built toolchains for the newly added cores and > run the tests on these cores it only means that new tests are > properly disabled for the cores without FPU/DFPU. I'll > take it as an independent build test (: Well it ran some xtensa tests thanks to the docker cross compiler support. Do you know what toolchains we need? Currently we have the following: ENV CPU_LIST csp dc232b dc233c ENV TOOLCHAIN_RELEASE 2018.02 RUN for cpu in $CPU_LIST; do \ curl -#SL http://github.com/foss-xtensa/toolchain/releases/download/$TOOLCHAIN_RELEASE/x86_64-$TOOLCHAIN_RELEASE-xtensa-$cpu-elf.tar.gz \ | tar -xzC /opt; \ done ENV PATH $PATH:/opt/$TOOLCHAIN_RELEASE/xtensa-dc232b-elf/bin:/opt/$TOOLCHAIN_RELEASE/xtensa-dc233c-elf/bin:/opt/$TOOLCHAIN_RELEASE/xtensa-csp-elf/bin -- Alex Bennée
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