Re: riscv: How to get more CSR information in debug trace?

[Alistair Francis]

On Fri, Jan 17, 2020 at 11:36 PM Ian Jiang <address@hidden> wrote:
>
> The following registers are given in QEMU debug trace with "-d cpu" parameter.
> pc       0000000000001000
> mhartid  0000000000000000
> mstatus  0000000000000000
> mip      0x0
> mie      0000000000000000
> mideleg  0000000000000000
> medeleg  0000000000000000
> mtvec    0000000000000000
> mepc     0000000000000000
> mcause   0000000000000000
>
> I want more information of other CSRs, such as sstatus, misa, pmpconfig0.
> How to get debug trace on all CSRs defined in RISC-V specification?

You can use the `info registers` command from the QEMU monitor.
Otherwise you could edit the source code to trace the registers you
are interested in.

The problem is there are so many CSRs we can't print them all.

Alistair

> Thanks!
>
> --
> Ian Jiang