riscv: How to get more CSR information in debug trace?

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riscv: How to get more CSR information in debug trace?

From:	Ian Jiang
Subject:	riscv: How to get more CSR information in debug trace?
Date:	Fri, 17 Jan 2020 21:32:55 +0800

The following registers are given in QEMU debug trace with "-d cpu" parameter.

pc 0000000000001000
mhartid 0000000000000000
mstatus 0000000000000000
mip 0x0
mie 0000000000000000
mideleg 0000000000000000
medeleg 0000000000000000
mtvec 0000000000000000
mepc 0000000000000000
mcause 0000000000000000

I want more information of other CSRs, such as sstatus, misa, pmpconfig0.

How to get debug trace on all CSRs defined in RISC-V specification?

Thanks!

Ian Jiang

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