[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 16/31] target/mips: Clean up handling of CP0 register
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 16/31] target/mips: Clean up handling of CP0 register 15 |
Date: |
Thu, 29 Aug 2019 12:24:58 +0200 |
From: Aleksandar Markovic <address@hidden>
Clean up handling of CP0 register 15.
Reviewed-by: Aleksandar Rikalo <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Message-Id: <address@hidden>
---
target/mips/cpu.h | 1 +
target/mips/translate.c | 20 ++++++++++----------
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 2a9c6d5..8ecfdb3 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -367,6 +367,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG15__EBASE 1
#define CP0_REG15__CDMMBASE 2
#define CP0_REG15__CMGCRBASE 3
+#define CP0_REG15__BEVVA 4
/* CP0 Register 16 */
#define CP0_REG16__CONFIG 0
#define CP0_REG16__CONFIG1 1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index efedced..238066f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7223,17 +7223,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
- case 0:
+ case CP0_REG15__PRID:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
register_name = "PRid";
break;
- case 1:
+ case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EBase";
break;
- case 3:
+ case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS32R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
@@ -7956,11 +7956,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
- case 0:
+ case CP0_REG15__PRID:
/* ignored */
register_name = "PRid";
break;
- case 1:
+ case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase";
@@ -8697,16 +8697,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
- case 0:
+ case CP0_REG15__PRID:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
register_name = "PRid";
break;
- case 1:
+ case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
register_name = "EBase";
break;
- case 3:
+ case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS32R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
@@ -9419,11 +9419,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
- case 0:
+ case CP0_REG15__PRID:
/* ignored */
register_name = "PRid";
break;
- case 1:
+ case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase";
--
2.7.4
- [Qemu-devel] [PULL 10/31] target/mips: Clean up handling of CP0 register 9, (continued)
- [Qemu-devel] [PULL 10/31] target/mips: Clean up handling of CP0 register 9, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 15/31] target/mips: Clean up handling of CP0 register 14, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 06/31] target/mips: Clean up handling of CP0 register 5, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 07/31] target/mips: Clean up handling of CP0 register 6, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 24/31] target/mips: Clean up handling of CP0 register 25, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 12/31] target/mips: Clean up handling of CP0 register 11, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 09/31] target/mips: Clean up handling of CP0 register 8, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 11/31] target/mips: Clean up handling of CP0 register 10, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 13/31] target/mips: Clean up handling of CP0 register 12, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 04/31] target/mips: Clean up handling of CP0 register 3, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 16/31] target/mips: Clean up handling of CP0 register 15,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 26/31] target/mips: Clean up handling of CP0 register 27, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 22/31] target/mips: Clean up handling of CP0 register 23, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 25/31] target/mips: Clean up handling of CP0 register 26, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 23/31] target/mips: Clean up handling of CP0 register 24, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 20/31] target/mips: Clean up handling of CP0 register 19, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 14/31] target/mips: Clean up handling of CP0 register 13, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 27/31] target/mips: Clean up handling of CP0 register 28, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 28/31] target/mips: Clean up handling of CP0 register 29, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 19/31] target/mips: Clean up handling of CP0 register 18, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 29/31] target/mips: Clean up handling of CP0 register 30, Aleksandar Markovic, 2019/08/29