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[Qemu-devel] [PULL 13/19] target/ppc: Refactor emulation of vmrgew and v
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 13/19] target/ppc: Refactor emulation of vmrgew and vmrgow instructions |
Date: |
Thu, 29 Aug 2019 16:08:21 +1000 |
From: Stefan Brankovic <address@hidden>
Since I found this two instructions implemented with tcg, I refactored
them so they are consistent with other similar implementations that
I introduced in this patch.
Also, a new dual macro GEN_VXFORM_TRANS_DUAL is added. This macro is
used if one instruction is realized with direct translation, and second
one with a helper.
Signed-off-by: Stefan Brankovic <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate/vmx-impl.inc.c | 66 ++++++++++++++++-------------
1 file changed, 37 insertions(+), 29 deletions(-)
diff --git a/target/ppc/translate/vmx-impl.inc.c
b/target/ppc/translate/vmx-impl.inc.c
index 0d71c10428..2472a5217a 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -350,6 +350,28 @@ static void glue(gen_, name0##_##name1)(DisasContext *ctx)
\
} \
}
+/*
+ * We use this macro if one instruction is realized with direct
+ * translation, and second one with helper.
+ */
+#define GEN_VXFORM_TRANS_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1)\
+static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
+{ \
+ if ((Rc(ctx->opcode) == 0) && \
+ ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ trans_##name0(ctx); \
+ } else if ((Rc(ctx->opcode) == 1) && \
+ ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
+ gen_##name1(ctx); \
+ } else { \
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
+ } \
+}
+
/* Adds support to provide invalid mask */
#define GEN_VXFORM_DUAL_EXT(name0, flg0, flg2_0, inval0, \
name1, flg1, flg2_1, inval1) \
@@ -431,20 +453,13 @@ GEN_VXFORM(vmrglb, 6, 4);
GEN_VXFORM(vmrglh, 6, 5);
GEN_VXFORM(vmrglw, 6, 6);
-static void gen_vmrgew(DisasContext *ctx)
+static void trans_vmrgew(DisasContext *ctx)
{
- TCGv_i64 tmp;
- TCGv_i64 avr;
- int VT, VA, VB;
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
- VT = rD(ctx->opcode);
- VA = rA(ctx->opcode);
- VB = rB(ctx->opcode);
- tmp = tcg_temp_new_i64();
- avr = tcg_temp_new_i64();
+ int VT = rD(ctx->opcode);
+ int VA = rA(ctx->opcode);
+ int VB = rB(ctx->opcode);
+ TCGv_i64 tmp = tcg_temp_new_i64();
+ TCGv_i64 avr = tcg_temp_new_i64();
get_avr64(avr, VB, true);
tcg_gen_shri_i64(tmp, avr, 32);
@@ -462,21 +477,14 @@ static void gen_vmrgew(DisasContext *ctx)
tcg_temp_free_i64(avr);
}
-static void gen_vmrgow(DisasContext *ctx)
+static void trans_vmrgow(DisasContext *ctx)
{
- TCGv_i64 t0, t1;
- TCGv_i64 avr;
- int VT, VA, VB;
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
- VT = rD(ctx->opcode);
- VA = rA(ctx->opcode);
- VB = rB(ctx->opcode);
- t0 = tcg_temp_new_i64();
- t1 = tcg_temp_new_i64();
- avr = tcg_temp_new_i64();
+ int VT = rD(ctx->opcode);
+ int VA = rA(ctx->opcode);
+ int VB = rB(ctx->opcode);
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 avr = tcg_temp_new_i64();
get_avr64(t0, VB, true);
get_avr64(t1, VA, true);
@@ -936,14 +944,14 @@ GEN_VXFORM_ENV(vminfp, 5, 17);
GEN_VXFORM_HETRO(vextublx, 6, 24)
GEN_VXFORM_HETRO(vextuhlx, 6, 25)
GEN_VXFORM_HETRO(vextuwlx, 6, 26)
-GEN_VXFORM_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
+GEN_VXFORM_TRANS_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
vextuwlx, PPC_NONE, PPC2_ISA300)
GEN_VXFORM_HETRO(vextubrx, 6, 28)
GEN_VXFORM_HETRO(vextuhrx, 6, 29)
GEN_VXFORM_HETRO(vextuwrx, 6, 30)
GEN_VXFORM_TRANS(lvsl, 6, 31)
GEN_VXFORM_TRANS(lvsr, 6, 32)
-GEN_VXFORM_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207, \
+GEN_VXFORM_TRANS_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207,
vextuwrx, PPC_NONE, PPC2_ISA300)
#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
--
2.21.0
- [Qemu-devel] [PULL 05/19] ppc/pnv: Introduce PowerNV machines with fixed CPU models, (continued)
- [Qemu-devel] [PULL 05/19] ppc/pnv: Introduce PowerNV machines with fixed CPU models, David Gibson, 2019/08/29
- [Qemu-devel] [PULL 01/19] ppc/pnv: Set default ram size to 1.75GB, David Gibson, 2019/08/29
- [Qemu-devel] [PULL 07/19] ppc: Fix xsmaddmdp and friends, David Gibson, 2019/08/29
- [Qemu-devel] [PULL 06/19] tests/boot-serial-test: add support for all the PowerNV machines, David Gibson, 2019/08/29
- [Qemu-devel] [PULL 11/19] target/ppc: Set float_tininess_before_rounding at cpu reset, David Gibson, 2019/08/29
- [Qemu-devel] [PULL 04/19] ppc/pnv: Generate phandle for the "interrupt-parent" property, David Gibson, 2019/08/29
- [Qemu-devel] [PULL 08/19] ppc: Fix xscvdpspn for SNAN, David Gibson, 2019/08/29
- [Qemu-devel] [PULL 10/19] pseries: Fix compat_pvr on reset, David Gibson, 2019/08/29
- [Qemu-devel] [PULL 09/19] spapr_pci: remove all child functions in function zero unplug, David Gibson, 2019/08/29
- [Qemu-devel] [PULL 12/19] target/ppc: Fix do_float_check_status vs inexact, David Gibson, 2019/08/29
- [Qemu-devel] [PULL 13/19] target/ppc: Refactor emulation of vmrgew and vmrgow instructions,
David Gibson <=
- [Qemu-devel] [PULL 18/19] spapr/pci: Convert types to QEMU coding style, David Gibson, 2019/08/29
- [Qemu-devel] [PULL 14/19] pseries: Update SLOF firmware image, David Gibson, 2019/08/29
- [Qemu-devel] [PULL 19/19] spapr: Set compat mode in spapr_core_plug(), David Gibson, 2019/08/29
- [Qemu-devel] [PULL 15/19] powerpc/spapr: Add host threads parameter to ibm, get_system_parameter, David Gibson, 2019/08/29
- [Qemu-devel] [PULL 16/19] spapr: Use SHUTDOWN_CAUSE_SUBSYSTEM_RESET for CAS reboots, David Gibson, 2019/08/29
- [Qemu-devel] [PULL 17/19] spapr_pci: Advertise BAR reallocation capability, David Gibson, 2019/08/29
- [Qemu-devel] [PULL 02/19] ppc/pnv: update skiboot to v6.4, David Gibson, 2019/08/29