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[Qemu-devel] [PATCH v3 69/69] target/arm: Inline gen_bx_im into callers
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 69/69] target/arm: Inline gen_bx_im into callers |
Date: |
Wed, 28 Aug 2019 12:04:56 -0700 |
There are only two remaining uses of gen_bx_im. In each case, we
know the destination mode -- not changing in the case of gen_jmp
or changing in the case of trans_BLX_i. Use this to simplify the
surrounding code.
For trans_BLX_i, use gen_jmp for the actual branch. For gen_jmp,
use gen_set_pc_im to set up the single-step.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 26 +++++++-------------------
1 file changed, 7 insertions(+), 19 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 5a9a6d3a1e..253f9f4142 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -765,21 +765,6 @@ static inline void gen_set_pc_im(DisasContext *s,
target_ulong val)
tcg_gen_movi_i32(cpu_R[15], val);
}
-/* Set PC and Thumb state from an immediate address. */
-static inline void gen_bx_im(DisasContext *s, uint32_t addr)
-{
- TCGv_i32 tmp;
-
- s->base.is_jmp = DISAS_JUMP;
- if (s->thumb != (addr & 1)) {
- tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, addr & 1);
- tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, thumb));
- tcg_temp_free_i32(tmp);
- }
- tcg_gen_movi_i32(cpu_R[15], addr & ~1);
-}
-
/* Set PC and Thumb state from var. var is marked as dead. */
static inline void gen_bx(DisasContext *s, TCGv_i32 var)
{
@@ -2706,9 +2691,8 @@ static inline void gen_jmp (DisasContext *s, uint32_t
dest)
{
if (unlikely(is_singlestepping(s))) {
/* An indirect jump so that we still trigger the debug exception. */
- if (s->thumb)
- dest |= 1;
- gen_bx_im(s, dest);
+ gen_set_pc_im(s, dest);
+ s->base.is_jmp = DISAS_JUMP;
} else {
gen_goto_tb(s, 0, dest);
}
@@ -10105,12 +10089,16 @@ static bool trans_BL(DisasContext *s, arg_i *a)
static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
{
+ TCGv_i32 tmp;
+
/* For A32, ARCH(5) is checked near the start of the uncond block. */
if (s->thumb && (a->imm & 2)) {
return false;
}
tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb);
- gen_bx_im(s, (read_pc(s) & ~3) + a->imm + !s->thumb);
+ tmp = tcg_const_i32(!s->thumb);
+ store_cpu_field(tmp, thumb);
+ gen_jmp(s, (read_pc(s) & ~3) + a->imm);
return true;
}
--
2.17.1
- [Qemu-devel] [PATCH v3 43/69] target/arm: Simplify disas_thumb2_insn, (continued)
- [Qemu-devel] [PATCH v3 43/69] target/arm: Simplify disas_thumb2_insn, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 55/69] target/arm: Convert T16 adjust sp (immediate), Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 49/69] target/arm: Convert T16 add pc/sp (immediate), Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 33/69] target/arm: Convert SVC, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 59/69] target/arm: Convert T16, nop hints, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 63/69] target/arm: Convert T16, Miscellaneous 16-bit instructions, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 35/69] target/arm: Convert Clear-Exclusive, Barriers, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 48/69] target/arm: Convert T16 load/store (immediate offset), Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 68/69] target/arm: Clean up disas_thumb_insn, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 69/69] target/arm: Inline gen_bx_im into callers,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 46/69] target/arm: Convert T16 data-processing (two low regs), Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 54/69] target/arm: Convert T16 add, compare, move (two high registers), Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 56/69] target/arm: Convert T16, extract, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 66/69] target/arm: Convert T16, Unconditional branch, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 62/69] target/arm: Convert T16, Conditional branches, Supervisor call, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 45/69] target/arm: Add skeleton for T16 decodetree, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 51/69] target/arm: Convert T16 add/sub (3 low, 2 low and imm), Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 52/69] target/arm: Convert T16 one low register and immediate, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 57/69] target/arm: Convert T16, Change processor state, Richard Henderson, 2019/08/28