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[Qemu-devel] [PATCH v3 54/69] target/arm: Convert T16 add, compare, move
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 54/69] target/arm: Convert T16 add, compare, move (two high registers) |
Date: |
Wed, 28 Aug 2019 12:04:41 -0700 |
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 49 ++----------------------------------------
target/arm/t16.decode | 10 +++++++++
2 files changed, 12 insertions(+), 47 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index cd39329e5c..cf19f1f777 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10722,55 +10722,10 @@ static void disas_thumb_insn(DisasContext *s,
uint32_t insn)
store_reg(s, rd, tmp);
break;
}
- if (insn & (1 << 10)) {
- /* 0b0100_01xx_xxxx_xxxx
- * - data processing extended, branch and exchange
- */
- rd = (insn & 7) | ((insn >> 4) & 8);
- rm = (insn >> 3) & 0xf;
- op = (insn >> 8) & 3;
- switch (op) {
- case 0: /* add */
- tmp = load_reg(s, rd);
- tmp2 = load_reg(s, rm);
- tcg_gen_add_i32(tmp, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- if (rd == 13) {
- /* ADD SP, SP, reg */
- store_sp_checked(s, tmp);
- } else {
- store_reg(s, rd, tmp);
- }
- break;
- case 1: /* cmp */
- tmp = load_reg(s, rd);
- tmp2 = load_reg(s, rm);
- gen_sub_CC(tmp, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- tcg_temp_free_i32(tmp);
- break;
- case 2: /* mov/cpy */
- tmp = load_reg(s, rm);
- if (rd == 13) {
- /* MOV SP, reg */
- store_sp_checked(s, tmp);
- } else {
- store_reg(s, rd, tmp);
- }
- break;
- case 3:
- /* 0b0100_0111_xxxx_xxxx
- * - branch [and link] exchange thumb register
- * In decodetree
- */
- goto illegal_op;
- }
- break;
- }
/*
- * 0b0100_00xx_xxxx_xxxx
- * - Data-processing (two low registers), in decodetree
+ * - Data-processing (two low registers), in decodetree
+ * - data processing extended, branch and exchange, in decodetree
*/
goto illegal_op;
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index edddbfb9b8..5a570484e3 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -146,6 +146,16 @@ CMP_xri 00101 ... ........ @arith_1i
s=1
ADD_rri 00110 ... ........ @arith_1i %s
SUB_rri 00111 ... ........ @arith_1i %s
+# Add, compare, move (two high registers)
+
+%reg_0_7 7:1 0:3
+@addsub_2h .... .... . rm:4 ... \
+ &s_rrr_shi rd=%reg_0_7 rn=%reg_0_7 shim=0 shty=0
+
+ADD_rrri 0100 0100 . .... ... @addsub_2h s=0
+CMP_xrri 0100 0101 . .... ... @addsub_2h s=1
+MOV_rxri 0100 0110 . .... ... @addsub_2h s=0
+
# Branch and exchange
@branchr .... .... . rm:4 ... &r
--
2.17.1
- [Qemu-devel] [PATCH v3 49/69] target/arm: Convert T16 add pc/sp (immediate), (continued)
- [Qemu-devel] [PATCH v3 49/69] target/arm: Convert T16 add pc/sp (immediate), Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 33/69] target/arm: Convert SVC, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 59/69] target/arm: Convert T16, nop hints, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 63/69] target/arm: Convert T16, Miscellaneous 16-bit instructions, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 35/69] target/arm: Convert Clear-Exclusive, Barriers, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 48/69] target/arm: Convert T16 load/store (immediate offset), Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 68/69] target/arm: Clean up disas_thumb_insn, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 69/69] target/arm: Inline gen_bx_im into callers, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 46/69] target/arm: Convert T16 data-processing (two low regs), Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 54/69] target/arm: Convert T16 add, compare, move (two high registers),
Richard Henderson <=
- [Qemu-devel] [PATCH v3 56/69] target/arm: Convert T16, extract, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 66/69] target/arm: Convert T16, Unconditional branch, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 62/69] target/arm: Convert T16, Conditional branches, Supervisor call, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 45/69] target/arm: Add skeleton for T16 decodetree, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 51/69] target/arm: Convert T16 add/sub (3 low, 2 low and imm), Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 52/69] target/arm: Convert T16 one low register and immediate, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 57/69] target/arm: Convert T16, Change processor state, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 53/69] target/arm: Convert T16 branch and exchange, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 64/69] target/arm: Convert T16, shift immediate, Richard Henderson, 2019/08/28