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[Qemu-devel] [PATCH v1 13/28] target/ricsv: Flush the TLB on virtulisati
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From: |
Alistair Francis |
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Subject: |
[Qemu-devel] [PATCH v1 13/28] target/ricsv: Flush the TLB on virtulisation mode changes |
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Date: |
Fri, 23 Aug 2019 16:38:23 -0700 |
To ensure our TLB isn't out-of-date we flush it on all virt mode
changes. Unlike priv mode this isn't saved in the mmu_idx as all
guests share V=1. The easiest option is just to flush on all changes.
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu_helper.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index afb3e8579e..8e8b156fc0 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -203,6 +203,11 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool
enable)
return;
}
+ /* Flush the TLB on all virt mode changes. */
+ if (((env->virt & VIRT_MODE_MASK) >> VIRT_MODE_SHIFT) != enable) {
+ tlb_flush(env_cpu(env));
+ }
+
env->virt &= ~VIRT_MODE_MASK;
env->virt |= enable << VIRT_MODE_SHIFT;
}
--
2.22.0
- [Qemu-devel] [PATCH v1 01/28] target/riscv: Add the Hypervisor extension, (continued)
- [Qemu-devel] [PATCH v1 01/28] target/riscv: Add the Hypervisor extension, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 04/28] target/riscv: Fix CSR perm checking for HS mode, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 03/28] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 05/28] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 06/28] target/riscv: Print priv and virt in disas log, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 08/28] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 07/28] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 09/28] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 12/28] target/riscv: Add support for virtual interrupt setting, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 11/28] target/riscv: Add background register swapping function, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 13/28] target/ricsv: Flush the TLB on virtulisation mode changes,
Alistair Francis <=
- [Qemu-devel] [PATCH v1 14/28] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 10/28] target/riscv: Convert mie and mstatus to pointers, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 16/28] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 15/28] riscv: plic: Always set sip.SEIP bit for HS, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 17/28] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 19/28] target/riscv: Disable guest FP support based on virtual status, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 18/28] target/riscv: Add hfence instructions, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 20/28] target/riscv: Mark both sstatus and vsstatus as dirty, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 21/28] target/riscv: Respect MPRV and SPRV for floating point ops, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 22/28] target/riscv: Allow specifying MMU stage, Alistair Francis, 2019/08/23