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[Qemu-devel] [PATCH v1 18/28] target/riscv: Add hfence instructions
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From: |
Alistair Francis |
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Subject: |
[Qemu-devel] [PATCH v1 18/28] target/riscv: Add hfence instructions |
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Date: |
Fri, 23 Aug 2019 16:38:36 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/insn32.decode | 23 ++++++-----
.../riscv/insn_trans/trans_privileged.inc.c | 40 +++++++++++++++++++
2 files changed, 54 insertions(+), 9 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 77f794ed70..cfd9ca6d2b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -63,20 +63,25 @@
@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
+@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
+@hfence_bvma ....... ..... ..... ... ..... ....... %rs2 %rs1
+
@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
@sfence_vm ....... ..... ..... ... ..... ....... %rs1
# *** Privileged Instructions ***
-ecall 000000000000 00000 000 00000 1110011
-ebreak 000000000001 00000 000 00000 1110011
-uret 0000000 00010 00000 000 00000 1110011
-sret 0001000 00010 00000 000 00000 1110011
-hret 0010000 00010 00000 000 00000 1110011
-mret 0011000 00010 00000 000 00000 1110011
-wfi 0001000 00101 00000 000 00000 1110011
-sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
-sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
+ecall 000000000000 00000 000 00000 1110011
+ebreak 000000000001 00000 000 00000 1110011
+uret 0000000 00010 00000 000 00000 1110011
+sret 0001000 00010 00000 000 00000 1110011
+hret 0010000 00010 00000 000 00000 1110011
+mret 0011000 00010 00000 000 00000 1110011
+wfi 0001000 00101 00000 000 00000 1110011
+hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
+hfence_bvma 0010001 ..... ..... 000 00000 1110011 @hfence_bvma
+sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
+sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
diff --git a/target/riscv/insn_trans/trans_privileged.inc.c
b/target/riscv/insn_trans/trans_privileged.inc.c
index c5e4b3e49a..b9b5a89b52 100644
--- a/target/riscv/insn_trans/trans_privileged.inc.c
+++ b/target/riscv/insn_trans/trans_privileged.inc.c
@@ -108,3 +108,43 @@ static bool trans_sfence_vm(DisasContext *ctx,
arg_sfence_vm *a)
#endif
return false;
}
+
+static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
+{
+#ifndef CONFIG_USER_ONLY
+ if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
+ has_ext(ctx, RVH)) {
+ /* Hpervisor extensions exist */
+ /*
+ * if (env->priv == PRV_M ||
+ * (env->priv == PRV_S &&
+ * !riscv_cpu_virt_enabled(env) &&
+ * get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
+ */
+ gen_helper_tlb_flush(cpu_env);
+ return true;
+ /* } */
+ }
+#endif
+ return false;
+}
+
+static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a)
+{
+#ifndef CONFIG_USER_ONLY
+ if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
+ has_ext(ctx, RVH)) {
+ /* Hpervisor extensions exist */
+ /*
+ * if (env->priv == PRV_M ||
+ * (env->priv == PRV_S &&
+ * !riscv_cpu_virt_enabled(env) &&
+ * get_field(ctx->mstatus_fs, MSTATUS_TVM))) {
+ */
+ gen_helper_tlb_flush(cpu_env);
+ return true;
+ /* } */
+ }
+#endif
+ return false;
+}
--
2.22.0
- [Qemu-devel] [PATCH v1 09/28] target/riscv: Add Hypervisor virtual CSRs accesses, (continued)
- [Qemu-devel] [PATCH v1 09/28] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 12/28] target/riscv: Add support for virtual interrupt setting, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 11/28] target/riscv: Add background register swapping function, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 13/28] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 14/28] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 10/28] target/riscv: Convert mie and mstatus to pointers, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 16/28] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 15/28] riscv: plic: Always set sip.SEIP bit for HS, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 17/28] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 19/28] target/riscv: Disable guest FP support based on virtual status, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 18/28] target/riscv: Add hfence instructions,
Alistair Francis <=
- [Qemu-devel] [PATCH v1 20/28] target/riscv: Mark both sstatus and vsstatus as dirty, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 21/28] target/riscv: Respect MPRV and SPRV for floating point ops, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 22/28] target/riscv: Allow specifying MMU stage, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 23/28] target/riscv: Allow specifying number of MMU stages, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 24/28] target/riscv: Implement second stage MMU, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 25/28] target/riscv: Call the second stage MMU in virtualisation mode, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 26/28] target/riscv: Add support for the 32-bit MSTATUSH CSR, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 27/28] target/riscv: Add the MSTATUS_MPV_ISSET helper macro, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 28/28] target/riscv: Allow enabling the Hypervisor extension, Alistair Francis, 2019/08/23