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[Qemu-devel] [PATCH v1 01/28] target/riscv: Add the Hypervisor extension
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From: |
Alistair Francis |
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Subject: |
[Qemu-devel] [PATCH v1 01/28] target/riscv: Add the Hypervisor extension |
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Date: |
Fri, 23 Aug 2019 16:37:52 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 124ed33ee4..7f54fb8c87 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -67,6 +67,7 @@
#define RVC RV('C')
#define RVS RV('S')
#define RVU RV('U')
+#define RVH RV('H')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
--
2.22.0
- [Qemu-devel] [PATCH v1 00/28] Add RISC-V Hypervisor Extension v0.4, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 02/28] target/riscv: Add the virtulisation mode, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 01/28] target/riscv: Add the Hypervisor extension,
Alistair Francis <=
- [Qemu-devel] [PATCH v1 04/28] target/riscv: Fix CSR perm checking for HS mode, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 03/28] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 05/28] target/riscv: Add the Hypervisor CSRs to CPUState, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 06/28] target/riscv: Print priv and virt in disas log, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 08/28] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 07/28] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/08/23
- [Qemu-devel] [PATCH v1 09/28] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2019/08/23