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[Qemu-devel] [PATCH v9 18/20] cputlb: Byte swap memory transaction attri
From: |
Tony Nguyen |
Subject: |
[Qemu-devel] [PATCH v9 18/20] cputlb: Byte swap memory transaction attribute |
Date: |
Sat, 24 Aug 2019 04:36:56 +1000 |
Notice new attribute, byte swap, and force the transaction through the
memory slow path.
Required by architectures that can invert endianness of memory
transaction, e.g. SPARC64 has the Invert Endian TTE bit.
Suggested-by: Richard Henderson <address@hidden>
Signed-off-by: Tony Nguyen <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
accel/tcg/cputlb.c | 11 +++++++++++
include/exec/memattrs.h | 2 ++
2 files changed, 13 insertions(+)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 3c9e634d99..f4573e2c7a 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -738,6 +738,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong
vaddr,
*/
address |= TLB_RECHECK;
}
+ if (attrs.byte_swap) {
+ address |= TLB_FORCE_SLOW;
+ }
if (!memory_region_is_ram(section->mr) &&
!memory_region_is_romd(section->mr)) {
/* IO memory case */
@@ -891,6 +894,10 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry
*iotlbentry,
bool locked = false;
MemTxResult r;
+ if (iotlbentry->attrs.byte_swap) {
+ op ^= MO_BSWAP;
+ }
+
section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
mr = section->mr;
mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
@@ -933,6 +940,10 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry
*iotlbentry,
bool locked = false;
MemTxResult r;
+ if (iotlbentry->attrs.byte_swap) {
+ op ^= MO_BSWAP;
+ }
+
section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
mr = section->mr;
mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index d4a3477d71..95f2d20d55 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -37,6 +37,8 @@ typedef struct MemTxAttrs {
unsigned int user:1;
/* Requester ID (for MSI for example) */
unsigned int requester_id:16;
+ /* Invert endianness for this page */
+ unsigned int byte_swap:1;
/*
* The following are target-specific page-table bits. These are not
* related to actual memory transactions at all. However, this structure
--
2.23.0
- [Qemu-devel] [PATCH v9 09/20] cputlb: Access MemoryRegion with MemOp, (continued)
- [Qemu-devel] [PATCH v9 09/20] cputlb: Access MemoryRegion with MemOp, Tony Nguyen, 2019/08/23
- [Qemu-devel] [PATCH v9 12/20] target/mips: Hard code size with MO_{8|16|32|64}, Tony Nguyen, 2019/08/23
- [Qemu-devel] [PATCH v9 11/20] hw/s390x: Hard code size with MO_{8|16|32|64}, Tony Nguyen, 2019/08/23
- [Qemu-devel] [PATCH v9 13/20] exec: Hard code size with MO_{8|16|32|64}, Tony Nguyen, 2019/08/23
- [Qemu-devel] [PATCH v9 17/20] cpu: TLB_FLAGS_MASK bit to force memory slow path, Tony Nguyen, 2019/08/23
- [Qemu-devel] [PATCH v9 15/20] cputlb: Replace size and endian operands for MemOp, Tony Nguyen, 2019/08/23
- [Qemu-devel] [PATCH v9 14/20] memory: Access MemoryRegion with endianness, Tony Nguyen, 2019/08/23
- [Qemu-devel] [PATCH v9 16/20] memory: Single byte swap along the I/O path, Tony Nguyen, 2019/08/23
- [Qemu-devel] [PATCH v9 18/20] cputlb: Byte swap memory transaction attribute,
Tony Nguyen <=
- [Qemu-devel] [PATCH v9 19/20] target/sparc: Add TLB entry with attributes, Tony Nguyen, 2019/08/23
- [Qemu-devel] [PATCH v9 20/20] target/sparc: sun4u Invert Endian TTE bit, Tony Nguyen, 2019/08/23