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[Qemu-devel] [PULL 06/42] target/ppc: Optimize emulation of lvsl and lvs
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 06/42] target/ppc: Optimize emulation of lvsl and lvsr instructions |
Date: |
Wed, 21 Aug 2019 17:25:06 +1000 |
From: Stefan Brankovic <address@hidden>
Adding simple macro that is calling tcg implementation of appropriate
instruction if altivec support is active.
Optimization of altivec instruction lvsl (Load Vector for Shift Left).
Place bytes sh:sh+15 of value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F
in destination register. Sh is calculated by adding 2 source registers and
getting bits 60-63 of result.
First, the bits [28-31] are placed from EA to variable sh. After that,
the bytes are created in the following way:
sh:(sh+7) of X(from description) by multiplying sh with 0x0101010101010101
followed by addition of the result with 0x0001020304050607. Value obtained
is placed in higher doubleword element of vD.
(sh+8):(sh+15) by adding the result of previous multiplication with
0x08090a0b0c0d0e0f. Value obtained is placed in lower doubleword element
of vD.
Optimization of altivec instruction lvsr (Load Vector for Shift Right).
Place bytes 16-sh:31-sh of value 0x00 || 0x01 || 0x02 || ... || 0x1E ||
0x1F in destination register. Sh is calculated by adding 2 source
registers and getting bits 60-63 of result.
First, the bits [28-31] are placed from EA to variable sh. After that,
the bytes are created in the following way:
sh:(sh+7) of X(from description) by multiplying sh with 0x0101010101010101
followed by substraction of the result from 0x1011121314151617. Value
obtained is placed in higher doubleword element of vD.
(sh+8):(sh+15) by substracting the result of previous multiplication from
0x18191a1b1c1d1e1f. Value obtained is placed in lower doubleword element
of vD.
Signed-off-by: Stefan Brankovic <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/helper.h | 2 -
target/ppc/int_helper.c | 18 -----
target/ppc/translate/vmx-impl.inc.c | 121 ++++++++++++++++++++--------
3 files changed, 89 insertions(+), 52 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 380c9b1e2a..121d7868d0 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -193,8 +193,6 @@ DEF_HELPER_2(vprtybw, void, avr, avr)
DEF_HELPER_2(vprtybd, void, avr, avr)
DEF_HELPER_2(vprtybq, void, avr, avr)
DEF_HELPER_3(vsubcuw, void, avr, avr, avr)
-DEF_HELPER_2(lvsl, void, avr, tl)
-DEF_HELPER_2(lvsr, void, avr, tl)
DEF_HELPER_FLAGS_5(vaddsbs, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
DEF_HELPER_FLAGS_5(vaddshs, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
DEF_HELPER_FLAGS_5(vaddsws, TCG_CALL_NO_RWG, void, avr, avr, avr, avr, i32)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 8f037af956..5dcca5362b 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -459,24 +459,6 @@ SATCVT(sd, uw, int64_t, uint32_t, 0, UINT32_MAX)
#undef SATCVT
#undef SATCVTU
-void helper_lvsl(ppc_avr_t *r, target_ulong sh)
-{
- int i, j = (sh & 0xf);
-
- for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
- r->VsrB(i) = j++;
- }
-}
-
-void helper_lvsr(ppc_avr_t *r, target_ulong sh)
-{
- int i, j = 0x10 - (sh & 0xf);
-
- for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
- r->VsrB(i) = j++;
- }
-}
-
void helper_mtvscr(CPUPPCState *env, uint32_t vscr)
{
env->vscr = vscr & ~(1u << VSCR_SAT);
diff --git a/target/ppc/translate/vmx-impl.inc.c
b/target/ppc/translate/vmx-impl.inc.c
index 663275b729..a9fe3c7834 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -142,38 +142,6 @@ GEN_VR_STVE(bx, 0x07, 0x04, 1);
GEN_VR_STVE(hx, 0x07, 0x05, 2);
GEN_VR_STVE(wx, 0x07, 0x06, 4);
-static void gen_lvsl(DisasContext *ctx)
-{
- TCGv_ptr rd;
- TCGv EA;
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
- EA = tcg_temp_new();
- gen_addr_reg_index(ctx, EA);
- rd = gen_avr_ptr(rD(ctx->opcode));
- gen_helper_lvsl(rd, EA);
- tcg_temp_free(EA);
- tcg_temp_free_ptr(rd);
-}
-
-static void gen_lvsr(DisasContext *ctx)
-{
- TCGv_ptr rd;
- TCGv EA;
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
- EA = tcg_temp_new();
- gen_addr_reg_index(ctx, EA);
- rd = gen_avr_ptr(rD(ctx->opcode));
- gen_helper_lvsr(rd, EA);
- tcg_temp_free(EA);
- tcg_temp_free_ptr(rd);
-}
-
static void gen_mfvscr(DisasContext *ctx)
{
TCGv_i32 t;
@@ -316,6 +284,16 @@ static void glue(gen_, name)(DisasContext *ctx)
\
tcg_temp_free_ptr(rd); \
}
+#define GEN_VXFORM_TRANS(name, opc2, opc3) \
+static void glue(gen_, name)(DisasContext *ctx) \
+{ \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ trans_##name(ctx); \
+}
+
#define GEN_VXFORM_ENV(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
@@ -515,6 +493,83 @@ static void gen_vmrgow(DisasContext *ctx)
tcg_temp_free_i64(avr);
}
+/*
+ * lvsl VRT,RA,RB - Load Vector for Shift Left
+ *
+ * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31].
+ * Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F.
+ * Bytes sh:sh+15 of X are placed into vD.
+ */
+static void trans_lvsl(DisasContext *ctx)
+{
+ int VT = rD(ctx->opcode);
+ TCGv_i64 result = tcg_temp_new_i64();
+ TCGv_i64 sh = tcg_temp_new_i64();
+ TCGv EA = tcg_temp_new();
+
+ /* Get sh(from description) by anding EA with 0xf. */
+ gen_addr_reg_index(ctx, EA);
+ tcg_gen_extu_tl_i64(sh, EA);
+ tcg_gen_andi_i64(sh, sh, 0xfULL);
+
+ /*
+ * Create bytes sh:sh+7 of X(from description) and place them in
+ * higher doubleword of vD.
+ */
+ tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL);
+ tcg_gen_addi_i64(result, sh, 0x0001020304050607ull);
+ set_avr64(VT, result, true);
+ /*
+ * Create bytes sh+8:sh+15 of X(from description) and place them in
+ * lower doubleword of vD.
+ */
+ tcg_gen_addi_i64(result, sh, 0x08090a0b0c0d0e0fULL);
+ set_avr64(VT, result, false);
+
+ tcg_temp_free_i64(result);
+ tcg_temp_free_i64(sh);
+ tcg_temp_free(EA);
+}
+
+/*
+ * lvsr VRT,RA,RB - Load Vector for Shift Right
+ *
+ * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31].
+ * Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F.
+ * Bytes (16-sh):(31-sh) of X are placed into vD.
+ */
+static void trans_lvsr(DisasContext *ctx)
+{
+ int VT = rD(ctx->opcode);
+ TCGv_i64 result = tcg_temp_new_i64();
+ TCGv_i64 sh = tcg_temp_new_i64();
+ TCGv EA = tcg_temp_new();
+
+
+ /* Get sh(from description) by anding EA with 0xf. */
+ gen_addr_reg_index(ctx, EA);
+ tcg_gen_extu_tl_i64(sh, EA);
+ tcg_gen_andi_i64(sh, sh, 0xfULL);
+
+ /*
+ * Create bytes (16-sh):(23-sh) of X(from description) and place them in
+ * higher doubleword of vD.
+ */
+ tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL);
+ tcg_gen_subfi_i64(result, 0x1011121314151617ULL, sh);
+ set_avr64(VT, result, true);
+ /*
+ * Create bytes (24-sh):(32-sh) of X(from description) and place them in
+ * lower doubleword of vD.
+ */
+ tcg_gen_subfi_i64(result, 0x18191a1b1c1d1e1fULL, sh);
+ set_avr64(VT, result, false);
+
+ tcg_temp_free_i64(result);
+ tcg_temp_free_i64(sh);
+ tcg_temp_free(EA);
+}
+
GEN_VXFORM(vmuloub, 4, 0);
GEN_VXFORM(vmulouh, 4, 1);
GEN_VXFORM(vmulouw, 4, 2);
@@ -662,6 +717,8 @@ GEN_VXFORM_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
GEN_VXFORM_HETRO(vextubrx, 6, 28)
GEN_VXFORM_HETRO(vextuhrx, 6, 29)
GEN_VXFORM_HETRO(vextuwrx, 6, 30)
+GEN_VXFORM_TRANS(lvsl, 6, 31)
+GEN_VXFORM_TRANS(lvsr, 6, 32)
GEN_VXFORM_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207, \
vextuwrx, PPC_NONE, PPC2_ISA300)
--
2.21.0
- [Qemu-devel] [PULL 00/42] ppc-for-4.2 queue 20190821, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 04/42] spapr_pci: Allow 2MiB and 16MiB IOMMU pagesizes by default, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 05/42] migration: Do not re-read the clock on pre_save in case of paused guest, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 02/42] spapr_iommu: Fix xlate trace to print translated address, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 01/42] spapr: quantify error messages regarding capability settings, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 11/42] target/ppc: Optimize emulation of vclzw instruction, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 10/42] target/ppc: Optimize emulation of vclzd instruction, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 03/42] hw: add compat machines for 4.2, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 06/42] target/ppc: Optimize emulation of lvsl and lvsr instructions,
David Gibson <=
- [Qemu-devel] [PULL 09/42] target/ppc: Optimize emulation of vgbbd instruction, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 08/42] target/ppc: move opcode decode tables to PowerPCCPU, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 19/42] docs/specs: initial spec summary for Ultravisor-related hcalls, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 07/42] target/ppc: Optimize emulation of vsl and vsr instructions, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 16/42] spapr: Implement H_PROD, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 15/42] spapr: Implement dispatch tracking for tcg, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 12/42] ppc: fix memory leak in spapr_caps_add_properties, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 13/42] ppc: fix memory leak in spapr_dt_drc(), David Gibson, 2019/08/21
- [Qemu-devel] [PULL 14/42] ppc: fix leak in h_client_architecture_support, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 26/42] ppc/xive: Provide unconditional escalation support, David Gibson, 2019/08/21