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[Qemu-devel] [PULL 11/42] target/ppc: Optimize emulation of vclzw instru
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 11/42] target/ppc: Optimize emulation of vclzw instruction |
Date: |
Wed, 21 Aug 2019 17:25:11 +1000 |
From: Stefan Brankovic <address@hidden>
Optimize Altivec instruction vclzw (Vector Count Leading Zeros Word).
This instruction counts the number of leading zeros of each word element
in source register and places result in the appropriate word element of
destination register.
Counting is to be performed in four iterations of for loop(one for each
word elemnt of source register vB). Every iteration consists of loading
appropriate word element from source register, counting leading zeros
with tcg_gen_clzi_i32, and saving the result in appropriate word element
of destination register.
Signed-off-by: Stefan Brankovic <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/helper.h | 1 -
target/ppc/int_helper.c | 3 ---
target/ppc/translate/vmx-impl.inc.c | 28 +++++++++++++++++++++++++++-
3 files changed, 27 insertions(+), 5 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index e203f76bf1..54ea9b9500 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -310,7 +310,6 @@ DEF_HELPER_4(vctsxs, void, env, avr, avr, i32)
DEF_HELPER_2(vclzb, void, avr, avr)
DEF_HELPER_2(vclzh, void, avr, avr)
-DEF_HELPER_2(vclzw, void, avr, avr)
DEF_HELPER_2(vctzb, void, avr, avr)
DEF_HELPER_2(vctzh, void, avr, avr)
DEF_HELPER_2(vctzw, void, avr, avr)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index b82765db33..46deb57a34 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1819,15 +1819,12 @@ VUPK(lsw, s64, s32, UPKLO)
#define clzb(v) ((v) ? clz32((uint32_t)(v) << 24) : 8)
#define clzh(v) ((v) ? clz32((uint32_t)(v) << 16) : 16)
-#define clzw(v) clz32((v))
VGENERIC_DO(clzb, u8)
VGENERIC_DO(clzh, u16)
-VGENERIC_DO(clzw, u32)
#undef clzb
#undef clzh
-#undef clzw
#define ctzb(v) ((v) ? ctz32(v) : 8)
#define ctzh(v) ((v) ? ctz32(v) : 16)
diff --git a/target/ppc/translate/vmx-impl.inc.c
b/target/ppc/translate/vmx-impl.inc.c
index 3372c2c3d3..0d71c10428 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -742,6 +742,32 @@ static void trans_vgbbd(DisasContext *ctx)
tcg_temp_free_i64(avr[1]);
}
+/*
+ * vclzw VRT,VRB - Vector Count Leading Zeros Word
+ *
+ * Counting the number of leading zero bits of each word element in source
+ * register and placing result in appropriate word element of destination
+ * register.
+ */
+static void trans_vclzw(DisasContext *ctx)
+{
+ int VT = rD(ctx->opcode);
+ int VB = rB(ctx->opcode);
+ TCGv_i32 tmp = tcg_temp_new_i32();
+ int i;
+
+ /* Perform count for every word element using tcg_gen_clzi_i32. */
+ for (i = 0; i < 4; i++) {
+ tcg_gen_ld_i32(tmp, cpu_env,
+ offsetof(CPUPPCState, vsr[32 + VB].u64[0]) + i * 4);
+ tcg_gen_clzi_i32(tmp, tmp, 32);
+ tcg_gen_st_i32(tmp, cpu_env,
+ offsetof(CPUPPCState, vsr[32 + VT].u64[0]) + i * 4);
+ }
+
+ tcg_temp_free_i32(tmp);
+}
+
/*
* vclzd VRT,VRB - Vector Count Leading Zeros Doubleword
*
@@ -1283,7 +1309,7 @@ GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
GEN_VXFORM_NOA(vclzb, 1, 28)
GEN_VXFORM_NOA(vclzh, 1, 29)
-GEN_VXFORM_NOA(vclzw, 1, 30)
+GEN_VXFORM_TRANS(vclzw, 1, 30)
GEN_VXFORM_TRANS(vclzd, 1, 31)
GEN_VXFORM_NOA_2(vnegw, 1, 24, 6)
GEN_VXFORM_NOA_2(vnegd, 1, 24, 7)
--
2.21.0
- [Qemu-devel] [PULL 00/42] ppc-for-4.2 queue 20190821, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 04/42] spapr_pci: Allow 2MiB and 16MiB IOMMU pagesizes by default, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 05/42] migration: Do not re-read the clock on pre_save in case of paused guest, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 02/42] spapr_iommu: Fix xlate trace to print translated address, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 01/42] spapr: quantify error messages regarding capability settings, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 11/42] target/ppc: Optimize emulation of vclzw instruction,
David Gibson <=
- [Qemu-devel] [PULL 10/42] target/ppc: Optimize emulation of vclzd instruction, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 03/42] hw: add compat machines for 4.2, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 06/42] target/ppc: Optimize emulation of lvsl and lvsr instructions, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 09/42] target/ppc: Optimize emulation of vgbbd instruction, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 08/42] target/ppc: move opcode decode tables to PowerPCCPU, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 19/42] docs/specs: initial spec summary for Ultravisor-related hcalls, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 07/42] target/ppc: Optimize emulation of vsl and vsr instructions, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 16/42] spapr: Implement H_PROD, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 15/42] spapr: Implement dispatch tracking for tcg, David Gibson, 2019/08/21
- [Qemu-devel] [PULL 12/42] ppc: fix memory leak in spapr_caps_add_properties, David Gibson, 2019/08/21