[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 26/29] target/arm: Use ror32 instead of open-coding t
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 26/29] target/arm: Use ror32 instead of open-coding the operation |
Date: |
Fri, 16 Aug 2019 14:17:16 +0100 |
From: Richard Henderson <address@hidden>
The helper function is more documentary, and also already
handles the case of rotate by zero.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index ebc7c67f025..02ce8d44fa1 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7964,8 +7964,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int
insn)
/* CPSR = immediate */
val = insn & 0xff;
shift = ((insn >> 8) & 0xf) * 2;
- if (shift)
- val = (val >> shift) | (val << (32 - shift));
+ val = ror32(val, shift);
i = ((insn & (1 << 22)) != 0);
if (gen_set_psr_im(s, msr_mask(s, (insn >> 16) & 0xf, i),
i, val)) {
@@ -8228,9 +8227,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int
insn)
/* immediate operand */
val = insn & 0xff;
shift = ((insn >> 8) & 0xf) * 2;
- if (shift) {
- val = (val >> shift) | (val << (32 - shift));
- }
+ val = ror32(val, shift);
tmp2 = tcg_temp_new_i32();
tcg_gen_movi_i32(tmp2, val);
if (logic_cc && shift) {
--
2.20.1
- [Qemu-devel] [PULL 15/29] target/arm: Use unallocated_encoding for aarch32, (continued)
- [Qemu-devel] [PULL 15/29] target/arm: Use unallocated_encoding for aarch32, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 12/29] target/arm: Replace offset with pc in gen_exception_insn, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 18/29] target/arm/cpu: Ensure we can use the pmu with kvm, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 20/29] target/arm/cpu: Use div-round-up to determine predicate register array size, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 21/29] target/arm/kvm64: Fix error returns, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 24/29] target/arm: Use tcg_gen_deposit_i32 for PKHBT, PKHTB, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 27/29] target/arm: Use tcg_gen_rotri_i32 for gen_swap_half, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 23/29] target/arm: Use tcg_gen_extract_i32 for shifter_out_im, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 25/29] target/arm: Remove redundant shift tests, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 22/29] target/arm/kvm64: Move the get/put of fpsimd registers out, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 26/29] target/arm: Use ror32 instead of open-coding the operation,
Peter Maydell <=
- [Qemu-devel] [PULL 28/29] target/arm: Simplify SMMLA, SMMLAR, SMMLS, SMMLSR, Peter Maydell, 2019/08/16
- [Qemu-devel] [PULL 29/29] target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word, Peter Maydell, 2019/08/16
- Re: [Qemu-devel] [PULL 00/29] target-arm queue, Peter Maydell, 2019/08/16