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Re: [Qemu-devel] [qemu-s390x] [PATCH-for-4.2 v2 6/6] s390x/mmu: Factor o
From: |
David Hildenbrand |
Subject: |
Re: [Qemu-devel] [qemu-s390x] [PATCH-for-4.2 v2 6/6] s390x/mmu: Factor out storage key handling |
Date: |
Wed, 14 Aug 2019 20:18:58 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.2 |
On 14.08.19 20:01, Thomas Huth wrote:
> On 8/14/19 9:23 AM, David Hildenbrand wrote:
>> Factor it out, add a comment how it all works, and also use it in the
>> REAL MMU.
>>
>> Reviewed-by: Cornelia Huck <address@hidden>
>> Signed-off-by: David Hildenbrand <address@hidden>
>> ---
>> target/s390x/mmu_helper.c | 113 +++++++++++++++++++++++---------------
>> 1 file changed, 69 insertions(+), 44 deletions(-)
>>
>> diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
>> index 6cc81a29b6..e125837d68 100644
>> --- a/target/s390x/mmu_helper.c
>> +++ b/target/s390x/mmu_helper.c
>> @@ -334,6 +334,73 @@ static int mmu_translate_asce(CPUS390XState *env,
>> target_ulong vaddr,
>> return r;
>> }
>>
>> +static void mmu_handle_skey(target_ulong addr, int rw, int *flags)
>> +{
>> + static S390SKeysClass *skeyclass;
>> + static S390SKeysState *ss;
>> + uint8_t key;
>> + int rc;
>> +
>> + if (unlikely(!ss)) {
>> + ss = s390_get_skeys_device();
>> + skeyclass = S390_SKEYS_GET_CLASS(ss);
>> + }
>> +
>> + /*
>> + * Whenever we create a new TLB entry, we set the storage key reference
>> + * bit. In case we allow write accesses, we set the storage key change
>> + * bit. Whenever the guest changes the storage key, we have to flush the
>> + * TLBs of all CPUs (the whole TLB or all affected entries), so that the
>> + * next reference/change will result in an MMU fault and make us
>> properly
>> + * update the storage key here.
>> + *
>> + * Note 1: "record of references ... is not necessarily accurate",
>> + * "change bit may be set in case no storing has occurred".
>> + * -> We can set reference/change bits even on exceptions.
>> + * Note 2: certain accesses seem to ignore storage keys. For example,
>> + * DAT translation does not set reference bits for table
>> accesses.
>> + *
>> + * TODO: key-controlled protection. Only CPU accesses make use of the
>> + * PSW key. CSS accesses are different - we have to pass in the
>> key.
>> + *
>> + * TODO: we have races between getting and setting the key.
>> + */
>> + if (addr < ram_size) {
>
> If you want to get rid of some indentation, you could do an early return
> if (addr >= ram_size) here instead.
Right, that makes a lot of sense, will do this. Thanks!
>
> Anyway, good idea to refactor this code, so also in its current shape:
>
> Reviewed-by: Thomas Huth <address@hidden>
>
--
Thanks,
David / dhildenb
- [Qemu-devel] [PATCH-for-4.2 v2 2/6] s390x/tcg: Rework MMU selection for instruction fetches, (continued)
- [Qemu-devel] [PATCH-for-4.2 v2 2/6] s390x/tcg: Rework MMU selection for instruction fetches, David Hildenbrand, 2019/08/14
- [Qemu-devel] [PATCH-for-4.2 v2 4/6] s390x/mmu: Trace the right value if setting/getting the storage key fails, David Hildenbrand, 2019/08/14
- [Qemu-devel] [PATCH-for-4.2 v2 5/6] s390x/mmu: Better storage key reference and change bit handling, David Hildenbrand, 2019/08/14
- [Qemu-devel] [PATCH-for-4.2 v2 6/6] s390x/mmu: Factor out storage key handling, David Hildenbrand, 2019/08/14
- Re: [Qemu-devel] [PATCH-for-4.2 v2 0/6] s390x/mmu: Storage key reference and change bit handling, Cornelia Huck, 2019/08/19