[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH v2] RISC-V: Ignore the S and U letters when form
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH v2] RISC-V: Ignore the S and U letters when formatting ISA strings |
Date: |
Wed, 14 Aug 2019 11:27:08 -0700 |
On Tue, Aug 13, 2019 at 3:54 PM Palmer Dabbelt <address@hidden> wrote:
>
> The ISA strings we're providing from QEMU aren't actually legal RISC-V
> ISA strings, as both S and U cannot exist as single-letter extensions
> and must instead be multi-letter strings. We're still using the ISA
> strings inside QEMU to track the availiable extensions, so this patch
> just strips out the S and U extensions when formatting ISA strings.
>
> This boots Linux on top of 4.1-rc3, which no longer has the U extension
> in /proc/cpuinfo.
>
> Signed-off-by: Palmer Dabbelt <address@hidden>
It looks like you are using tabs in here, once they are removed:
Reviewed-by: Alistair Francis <address@hidden>
Alistair
> ---
> target/riscv/cpu.c | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index f8d07bd20ad7..a67c54c738ba 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -501,7 +501,23 @@ char *riscv_isa_string(RISCVCPU *cpu)
> char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
> for (i = 0; i < sizeof(riscv_exts); i++) {
> if (cpu->env.misa & RV(riscv_exts[i])) {
> - *p++ = qemu_tolower(riscv_exts[i]);
> + char lower = qemu_tolower(riscv_exts[i]);
> + switch (lower) {
> + case 's':
> + case 'u':
> + /*
> + * The 's' and 'u' letters shouldn't show up in ISA strings as
> + * they're not extensions, but they should show up in MISA.
> + * Since we use these letters interally as a pseudo ISA string
> + * to set MISA it's easier to just strip them out when
> + * formatting the ISA string.
> + */
> + break;
> +
> + default:
> + *p++ = lower;
> + break;
> + }
> }
> }
> *p = '\0';
> --
> 2.21.0
>
>