[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH v3 19/28] riscv: sifive_u: Instantiate OTP memor
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH v3 19/28] riscv: sifive_u: Instantiate OTP memory with a serial number |
Date: |
Sun, 11 Aug 2019 10:13:11 -0700 |
On Sun, Aug 11, 2019 at 1:13 AM Bin Meng <address@hidden> wrote:
>
> This adds an OTP memory with a given serial number to the sifive_u
> machine. With such support, the upstream U-Boot for sifive_fu540
> boots out of the box on the sifive_u machine.
>
> Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> hw/riscv/sifive_u.c | 5 +++++
> include/hw/riscv/sifive_u.h | 1 +
> 2 files changed, 6 insertions(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 5022b8f..486b247 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -10,6 +10,7 @@
> * 1) CLINT (Core Level Interruptor)
> * 2) PLIC (Platform Level Interrupt Controller)
> * 3) PRCI (Power, Reset, Clock, Interrupt)
> + * 4) OTP (One-Time Programmable) memory with stored serial number
> *
> * This board currently generates devicetree dynamically that indicates at
> least
> * two harts and up to five harts.
> @@ -43,6 +44,7 @@
> #include "hw/riscv/sifive_clint.h"
> #include "hw/riscv/sifive_uart.h"
> #include "hw/riscv/sifive_u.h"
> +#include "hw/riscv/sifive_u_otp.h"
> #include "hw/riscv/sifive_u_prci.h"
> #include "hw/riscv/boot.h"
> #include "chardev/char.h"
> @@ -65,10 +67,12 @@ static const struct MemmapEntry {
> [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
> [SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
> [SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
> + [SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
> [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
> [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 },
> };
>
> +#define SIFIVE_OTP_SERIAL 1
> #define GEM_REVISION 0x10070109
>
> static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> @@ -441,6 +445,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev,
> Error **errp)
> memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
> SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
> sifive_u_prci_create(memmap[SIFIVE_U_PRCI].base);
> + sifive_u_otp_create(memmap[SIFIVE_U_OTP].base, SIFIVE_OTP_SERIAL);
>
> for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
> plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index e318ecb..3ae75b5 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -54,6 +54,7 @@ enum {
> SIFIVE_U_PRCI,
> SIFIVE_U_UART0,
> SIFIVE_U_UART1,
> + SIFIVE_U_OTP,
> SIFIVE_U_DRAM,
> SIFIVE_U_GEM
> };
> --
> 2.7.4
>
>
- [Qemu-devel] [PATCH v3 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, (continued)
- [Qemu-devel] [PATCH v3 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 13/28] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 14/28] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 17/28] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 16/28] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 18/28] riscv: hw: Implement a model for SiFive FU540 OTP, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 19/28] riscv: sifive_u: Instantiate OTP memory with a serial number, Bin Meng, 2019/08/11
- Re: [Qemu-devel] [PATCH v3 19/28] riscv: sifive_u: Instantiate OTP memory with a serial number,
Alistair Francis <=
- [Qemu-devel] [PATCH v3 21/28] riscv: sifive_u: Update UART and ethernet node clock properties, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 22/28] riscv: sifive_u: Generate an aliases node in the device tree, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 23/28] riscv: sifive_u: Fix broken GEM support, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 24/28] riscv: sifive_u: Support loading initramfs, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 25/28] riscv: hw: Remove not needed PLIC properties in device tree, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 27/28] riscv: virt: Change create_fdt() to return void, Bin Meng, 2019/08/11