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[Qemu-devel] [PATCH v3 25/28] riscv: hw: Remove not needed PLIC properti
From: |
Bin Meng |
Subject: |
[Qemu-devel] [PATCH v3 25/28] riscv: hw: Remove not needed PLIC properties in device tree |
Date: |
Sun, 11 Aug 2019 01:06:58 -0700 |
This removes "reg-names" and "riscv,max-priority" properties of the
PLIC node from device tree.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Jonathan Behrens <address@hidden>
---
Changes in v3: None
Changes in v2:
- keep the PLIC compatible string unchanged as OpenSBI uses that
for DT fix up
hw/riscv/sifive_u.c | 2 --
hw/riscv/virt.c | 2 --
2 files changed, 4 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index b0026aa..8801ee2 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -238,8 +238,6 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_cells(fdt, nodename, "reg",
0x0, memmap[SIFIVE_U_PLIC].base,
0x0, memmap[SIFIVE_U_PLIC].size);
- qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
- qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 127f005..2f75195 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -244,8 +244,6 @@ static void *create_fdt(RISCVVirtState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_cells(fdt, nodename, "reg",
0x0, memmap[VIRT_PLIC].base,
0x0, memmap[VIRT_PLIC].size);
- qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
- qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
--
2.7.4
- [Qemu-devel] [PATCH v3 18/28] riscv: hw: Implement a model for SiFive FU540 OTP, (continued)
- [Qemu-devel] [PATCH v3 18/28] riscv: hw: Implement a model for SiFive FU540 OTP, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 19/28] riscv: sifive_u: Instantiate OTP memory with a serial number, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 21/28] riscv: sifive_u: Update UART and ethernet node clock properties, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 22/28] riscv: sifive_u: Generate an aliases node in the device tree, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 23/28] riscv: sifive_u: Fix broken GEM support, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 24/28] riscv: sifive_u: Support loading initramfs, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 25/28] riscv: hw: Remove not needed PLIC properties in device tree,
Bin Meng <=
- [Qemu-devel] [PATCH v3 27/28] riscv: virt: Change create_fdt() to return void, Bin Meng, 2019/08/11
- [Qemu-devel] [PATCH v3 28/28] riscv: sifive_u: Update model and compatible strings in device tree, Bin Meng, 2019/08/11
- Re: [Qemu-devel] [PATCH v3 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine, Bin Meng, 2019/08/11