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Re: [Qemu-devel] [PATCH 17/28] riscv: sifive_u: Change UART node name in
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH 17/28] riscv: sifive_u: Change UART node name in device tree |
Date: |
Mon, 5 Aug 2019 17:20:57 -0700 |
On Mon, Aug 5, 2019 at 9:05 AM Bin Meng <address@hidden> wrote:
>
> OpenSBI for fu540 does DT fix up (see fu540_modify_dt()) by updating
> chosen "stdout-path" to point to "/soc/serial@...", and U-Boot will
> use this information to locate the serial node and probe its driver.
> However currently we generate the UART node name as "/soc/uart@...",
> causing U-Boot fail to find the serial node in DT.
>
> Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 20dee52..8044166 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -273,7 +273,7 @@ static void create_fdt(SiFiveUState *s, const struct
> MemmapEntry *memmap,
> qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
> g_free(nodename);
>
> - nodename = g_strdup_printf("/soc/uart@%lx",
> + nodename = g_strdup_printf("/soc/serial@%lx",
> (long)memmap[SIFIVE_U_UART0].base);
> qemu_fdt_add_subnode(fdt, nodename);
> qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
> --
> 2.7.4
>
>
- [Qemu-devel] [PATCH 21/28] riscv: sifive_u: Update UART and ethernet node clock properties, (continued)
- [Qemu-devel] [PATCH 21/28] riscv: sifive_u: Update UART and ethernet node clock properties, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 23/28] riscv: sifive: Move sifive_mmio_emulate() to a common place, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 13/28] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 18/28] riscv: hw: Implement a model for SiFive FU540 OTP, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 16/28] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 17/28] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/08/05
- Re: [Qemu-devel] [PATCH 17/28] riscv: sifive_u: Change UART node name in device tree,
Alistair Francis <=
- [Qemu-devel] [PATCH 22/28] riscv: sifive_u: Generate an aliases node in the device tree, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 24/28] riscv: sifive_u: Fix broken GEM support, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 25/28] riscv: sifive_u: Support loading initramfs, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 27/28] riscv: virt: Change create_fdt() to return void, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 28/28] riscv: sifive_u: Update model and compatible strings in device tree, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 26/28] riscv: hw: Update PLIC device tree, Bin Meng, 2019/08/05