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[Qemu-devel] [PATCH 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccf
From: |
Bin Meng |
Subject: |
[Qemu-devel] [PATCH 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming |
Date: |
Mon, 5 Aug 2019 09:00:07 -0700 |
It should use SIFIVE_PRCI_HFXOSCCFG_RDY and SIFIVE_PRCI_HFXOSCCFG_EN
for hfxosccfg register programming.
Signed-off-by: Bin Meng <address@hidden>
---
hw/riscv/sifive_e_prci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c
index acb914d..c906f11 100644
--- a/hw/riscv/sifive_e_prci.c
+++ b/hw/riscv/sifive_e_prci.c
@@ -89,7 +89,7 @@ static void sifive_prci_init(Object *obj)
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
s->hfrosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN);
- s->hfxosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN);
+ s->hfxosccfg = (SIFIVE_PRCI_HFXOSCCFG_RDY | SIFIVE_PRCI_HFXOSCCFG_EN);
s->pllcfg = (SIFIVE_PRCI_PLLCFG_REFSEL | SIFIVE_PRCI_PLLCFG_BYPASS |
SIFIVE_PRCI_PLLCFG_LOCK);
s->plloutdiv = SIFIVE_PRCI_PLLOUTDIV_DIV1;
--
2.7.4
- [Qemu-devel] [PATCH 10/28] riscv: sifive_u: Remove the unnecessary include of prci header, (continued)
- [Qemu-devel] [PATCH 10/28] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 21/28] riscv: sifive_u: Update UART and ethernet node clock properties, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 23/28] riscv: sifive: Move sifive_mmio_emulate() to a common place, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 13/28] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 18/28] riscv: hw: Implement a model for SiFive FU540 OTP, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 16/28] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming,
Bin Meng <=
- [Qemu-devel] [PATCH 17/28] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 22/28] riscv: sifive_u: Generate an aliases node in the device tree, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 24/28] riscv: sifive_u: Fix broken GEM support, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 25/28] riscv: sifive_u: Support loading initramfs, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 27/28] riscv: virt: Change create_fdt() to return void, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 28/28] riscv: sifive_u: Update model and compatible strings in device tree, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 26/28] riscv: hw: Update PLIC device tree, Bin Meng, 2019/08/05