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[Qemu-commits] [qemu/qemu] ab0c94: target/i386: Add Denverton-v2 (no MPX

From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] ab0c94: target/i386: Add Denverton-v2 (no MPX) CPU model
Date: Thu, 19 Mar 2020 08:30:14 -0700 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: ab0c942c868210e78ff88aef83efb4b4018068e1
      
https://github.com/qemu/qemu/commit/ab0c942c868210e78ff88aef83efb4b4018068e1
  Author: Tao Xu <address@hidden>
  Date:   2020-03-17 (Tue, 17 Mar 2020)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  target/i386: Add Denverton-v2 (no MPX) CPU model

Because MPX is being removed from the linux kernel, remove MPX feature
from Denverton.

Signed-off-by: Tao Xu <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: c63938df0aaa307771214d1152d5e1ade3e3b730
      
https://github.com/qemu/qemu/commit/c63938df0aaa307771214d1152d5e1ade3e3b730
  Author: Tao Xu <address@hidden>
  Date:   2020-03-17 (Tue, 17 Mar 2020)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  target/i386: Add new property note to versioned CPU models

Add additional information for -cpu help to indicate the changes in this
version of CPU model.

Suggested-by: Eduardo Habkost <address@hidden>
Signed-off-by: Tao Xu <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: a16e8dbc043720abcb37fc7dca313e720b4e0f0c
      
https://github.com/qemu/qemu/commit/a16e8dbc043720abcb37fc7dca313e720b4e0f0c
  Author: Moger, Babu <address@hidden>
  Date:   2020-03-17 (Tue, 17 Mar 2020)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  i386: Add missing cpu feature bits in EPYC model

Adds the following missing CPUID bits:
perfctr-core : core performance counter extensions support. Enables the VM
               to use extended performance counter support. It enables six
               programmable counters instead of 4 counters.
clzero       : instruction zeroes out the 64 byte cache line specified in RAX.
xsaveerptr   : XSAVE, XSAVE, FXSAVEOPT, XSAVEC, XSAVES always save error
               pointers and FXRSTOR, XRSTOR, XRSTORS always restore error
               pointers.
ibpb         : Indirect Branch Prediction Barrie.
xsaves       : XSAVES, XRSTORS and IA32_XSS supported.

Depends on following kernel commits:
40bc47b08b6e ("kvm: x86: Enumerate support for CLZERO instruction")
504ce1954fba ("KVM: x86: Expose XSAVEERPTR to the guest")
52297436199d ("kvm: svm: Update svm_xsaves_supported")

These new features will be added in EPYC-v3. The -cpu help output after the 
change.
x86 EPYC-v1               AMD EPYC Processor
x86 EPYC-v2               AMD EPYC Processor (with IBPB)
x86 EPYC-v3               AMD EPYC Processor

Signed-off-by: Babu Moger <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 143c30d4d346831a09e59e9af45afdca0331e819
      
https://github.com/qemu/qemu/commit/143c30d4d346831a09e59e9af45afdca0331e819
  Author: Moger, Babu <address@hidden>
  Date:   2020-03-17 (Tue, 17 Mar 2020)

  Changed paths:
    M target/i386/cpu.c
    M target/i386/cpu.h

  Log Message:
  -----------
  i386: Add 2nd Generation AMD EPYC processors

Adds the support for 2nd Gen AMD EPYC Processors. The model display
name will be EPYC-Rome.

Adds the following new feature bits on top of the feature bits from the
first generation EPYC models.
perfctr-core : core performance counter extensions support. Enables the VM to
               use extended performance counter support. It enables six
               programmable counters instead of four counters.
clzero       : instruction zeroes out the 64 byte cache line specified in RAX.
xsaveerptr   : XSAVE, XSAVE, FXSAVEOPT, XSAVEC, XSAVES always save error
               pointers and FXRSTOR, XRSTOR, XRSTORS always restore error
               pointers.
wbnoinvd     : Write back and do not invalidate cache
ibpb         : Indirect Branch Prediction Barrier
amd-stibp    : Single Thread Indirect Branch Predictor
clwb         : Cache Line Write Back and Retain
xsaves       : XSAVES, XRSTORS and IA32_XSS support
rdpid        : Read Processor ID instruction support
umip         : User-Mode Instruction Prevention support

The  Reference documents are available at
https://developer.amd.com/wp-content/resources/55803_0.54-PUB.pdf
https://www.amd.com/system/files/TechDocs/24594.pdf

Depends on following kernel commits:
40bc47b08b6e ("kvm: x86: Enumerate support for CLZERO instruction")
504ce1954fba ("KVM: x86: Expose XSAVEERPTR to the guest")
6d61e3c32248 ("kvm: x86: Expose RDPID in KVM_GET_SUPPORTED_CPUID")
52297436199d ("kvm: svm: Update svm_xsaves_supported")

Signed-off-by: Babu Moger <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: dcf08bc60bcce8237e42ee9d4c4983ed98401b8a
      
https://github.com/qemu/qemu/commit/dcf08bc60bcce8237e42ee9d4c4983ed98401b8a
  Author: Babu Moger <address@hidden>
  Date:   2020-03-17 (Tue, 17 Mar 2020)

  Changed paths:
    M hw/i386/pc.c
    M hw/i386/x86.c
    M include/hw/i386/topology.h

  Log Message:
  -----------
  hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs

Rename few data structures related to X86 topology.  X86CPUTopoIDs will
have individual arch ids. Next patch introduces X86CPUTopoInfo which will
have all topology information(like cores, threads etc..).

Signed-off-by: Babu Moger <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 4ba59be1d6d8c57941841a505cb4656628d582d0
      
https://github.com/qemu/qemu/commit/4ba59be1d6d8c57941841a505cb4656628d582d0
  Author: Dr. David Alan Gilbert <address@hidden>
  Date:   2020-03-17 (Tue, 17 Mar 2020)

  Changed paths:
    M hw/core/machine.c

  Log Message:
  -----------
  machine/memory encryption: Disable mem merge

When a host is running with memory encryption, the memory isn't visible
to the host kernel; attempts to merge that memory are futile because
what it's really comparing is encrypted memory, usually encrypted
with different keys.

Automatically turn mem-merge off when memory encryption is specified.

https://bugzilla.redhat.com/show_bug.cgi?id=1796356

Signed-off-by: Dr. David Alan Gilbert <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 781c67ca5585b38a29076093ecdff4f273db5a35
      
https://github.com/qemu/qemu/commit/781c67ca5585b38a29076093ecdff4f273db5a35
  Author: Peter Maydell <address@hidden>
  Date:   2020-03-17 (Tue, 17 Mar 2020)

  Changed paths:
    M hw/core/cpu.c
    M include/hw/core/cpu.h
    A scripts/coccinelle/cpu-reset.cocci
    M target/alpha/cpu-qom.h
    M target/arm/cpu-qom.h
    M target/arm/cpu.c
    M target/cris/cpu-qom.h
    M target/cris/cpu.c
    M target/hppa/cpu-qom.h
    M target/i386/cpu-qom.h
    M target/i386/cpu.c
    M target/lm32/cpu-qom.h
    M target/lm32/cpu.c
    M target/m68k/cpu-qom.h
    M target/m68k/cpu.c
    M target/microblaze/cpu-qom.h
    M target/microblaze/cpu.c
    M target/mips/cpu-qom.h
    M target/mips/cpu.c
    M target/moxie/cpu.c
    M target/moxie/cpu.h
    M target/nios2/cpu.c
    M target/nios2/cpu.h
    M target/openrisc/cpu.c
    M target/openrisc/cpu.h
    M target/ppc/cpu-qom.h
    M target/ppc/translate_init.inc.c
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/s390x/cpu-qom.h
    M target/s390x/cpu.c
    M target/sh4/cpu-qom.h
    M target/sh4/cpu.c
    M target/sparc/cpu-qom.h
    M target/sparc/cpu.c
    M target/tilegx/cpu.c
    M target/tilegx/cpu.h
    M target/tricore/cpu-qom.h
    M target/tricore/cpu.c
    M target/xtensa/cpu-qom.h
    M target/xtensa/cpu.c

  Log Message:
  -----------
  cpu: Use DeviceClass reset instead of a special CPUClass reset

The CPUClass has a 'reset' method.  This is a legacy from when
TYPE_CPU used not to inherit from TYPE_DEVICE.  We don't need it any
more, as we can simply use the TYPE_DEVICE reset.  The 'cpu_reset()'
function is kept as the API which most places use to reset a CPU; it
is now a wrapper which calls device_cold_reset() and then the
tracepoint function.

This change should not cause CPU objects to be reset more often
than they are at the moment, because:
 * nobody is directly calling device_cold_reset() or
   qdev_reset_all() on CPU objects
 * no CPU object is on a qbus, so they will not be reset either
   by somebody calling qbus_reset_all()/bus_cold_reset(), or
   by the main "reset sysbus and everything in the qbus tree"
   reset that most devices are reset by

Note that this does not change the need for each machine or whatever
to use qemu_register_reset() to arrange to call cpu_reset() -- that
is necessary because CPU objects are not on any qbus, so they don't
get reset when the qbus tree rooted at the sysbus bus is reset, and
this isn't being changed here.

All the changes to the files under target/ were made using the
included Coccinelle script, except:

(1) the deletion of the now-inaccurate and not terribly useful
"CPUClass::reset" comments was done with a perl one-liner afterwards:
  perl -n -i -e '/ CPUClass::reset/ or print' target/*/*.c

(2) this bit of the s390 change was done by hand, because the
Coccinelle script is not sophisticated enough to handle the
parent_reset call being inside another function:

| @@ -96,8 +96,9 @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type)
|     S390CPU *cpu = S390_CPU(s);
|     S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
|     CPUS390XState *env = &cpu->env;
|+    DeviceState *dev = DEVICE(s);
|
|-    scc->parent_reset(s);
|+    scc->parent_reset(dev);
|     cpu->env.sigp_order = 0;
|     s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu);

Signed-off-by: Peter Maydell <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 53a5e7bddf2a6299e4efdba9ad4f69e1c8f401b0
      
https://github.com/qemu/qemu/commit/53a5e7bddf2a6299e4efdba9ad4f69e1c8f401b0
  Author: Babu Moger <address@hidden>
  Date:   2020-03-17 (Tue, 17 Mar 2020)

  Changed paths:
    M hw/i386/pc.c
    M hw/i386/x86.c
    M include/hw/i386/topology.h
    M include/hw/i386/x86.h
    M tests/test-x86-cpuid.c

  Log Message:
  -----------
  hw/i386: Introduce X86CPUTopoInfo to contain topology info

This is an effort to re-arrange few data structure for better readability.

1. Add X86CPUTopoInfo which will have all the topology informations
   required to build the cpu topology. There is no functional changes.

2. Introduce init_topo_info to initialize X86CPUTopoInfo members from
   X86MachineState.

3. Update x86 unit tests for new calling convention with parameter 
X86CPUTopoInfo

There is no functional changes.

Signed-off-by: Babu Moger <address@hidden>
Message-Id: <address@hidden>


  Commit: f20dec0b638d1ebb4ef2f71d51ea1c540402bc7c
      
https://github.com/qemu/qemu/commit/f20dec0b638d1ebb4ef2f71d51ea1c540402bc7c
  Author: Babu Moger <address@hidden>
  Date:   2020-03-17 (Tue, 17 Mar 2020)

  Changed paths:
    M include/hw/i386/topology.h
    M target/i386/cpu.c
    M tests/test-x86-cpuid.c

  Log Message:
  -----------
  hw/i386: Consolidate topology functions

Now that we have all the parameters in X86CPUTopoInfo, we can just
pass the structure to calculate the offsets and width.

Signed-off-by: Babu Moger <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Acked-by: Michael S. Tsirkin <address@hidden>
Message-Id: <address@hidden>


  Commit: 8cb30e3aec07cb85fe424191e37cf983a2ac5416
      
https://github.com/qemu/qemu/commit/8cb30e3aec07cb85fe424191e37cf983a2ac5416
  Author: Babu Moger <address@hidden>
  Date:   2020-03-17 (Tue, 17 Mar 2020)

  Changed paths:
    M hw/core/machine.c
    M hw/i386/pc.c
    M include/hw/boards.h
    M softmmu/vl.c

  Log Message:
  -----------
  machine: Add SMP Sockets in CpuTopology

Store the  smp sockets in CpuTopology. The socket information required to
build the apic id in EPYC mode. Right now socket information is not passed
to down when decoding the apic id. Add the socket information here.

Signed-off-by: Babu Moger <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Acked-by: Michael S. Tsirkin <address@hidden>
Message-Id: <address@hidden>


  Commit: 156778a08314dd224e675acee7975ec2354e68e5
      
https://github.com/qemu/qemu/commit/156778a08314dd224e675acee7975ec2354e68e5
  Author: Babu Moger <address@hidden>
  Date:   2020-03-17 (Tue, 17 Mar 2020)

  Changed paths:
    M hw/i386/x86.c

  Log Message:
  -----------
  hw/i386: Remove unnecessary initialization in x86_cpu_new

The function pc_cpu_pre_plug takes care of initialization of CPUX86State.
So, remove the initialization here.

Suggested-by: Igor Mammedov <address@hidden>
Signed-off-by: Babu Moger <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Acked-by: Michael S. Tsirkin <address@hidden>
Message-Id: <address@hidden>


  Commit: c24a41bb53c0854d22c96b30d57cfcaa543c409d
      
https://github.com/qemu/qemu/commit/c24a41bb53c0854d22c96b30d57cfcaa543c409d
  Author: Babu Moger <address@hidden>
  Date:   2020-03-17 (Tue, 17 Mar 2020)

  Changed paths:
    M hw/i386/pc.c
    M hw/i386/x86.c
    M include/hw/i386/topology.h
    M target/i386/cpu.c
    M target/i386/cpu.h
    M tests/test-x86-cpuid.c

  Log Message:
  -----------
  hw/i386: Update structures to save the number of nodes per package

Update structures X86CPUTopoIDs and CPUX86State to hold the number of
nodes per package. This is required to build EPYC mode topology.

Signed-off-by: Babu Moger <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Acked-by: Michael S. Tsirkin <address@hidden>
Message-Id: <address@hidden>


  Commit: 3c6712eca07255803b61ca3d632f61a65c078c36
      
https://github.com/qemu/qemu/commit/3c6712eca07255803b61ca3d632f61a65c078c36
  Author: Babu Moger <address@hidden>
  Date:   2020-03-17 (Tue, 17 Mar 2020)

  Changed paths:
    M hw/i386/pc.c
    M include/hw/i386/topology.h

  Log Message:
  -----------
  hw/i386: Rename apicid_from_topo_ids to x86_apicid_from_topo_ids

For consistency rename apicid_from_topo_ids to x86_apicid_from_topo_ids.
No functional change.

Signed-off-by: Babu Moger <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Acked-by: Michael S. Tsirkin <address@hidden>
Message-Id: <address@hidden>


  Commit: 4dd6517e369828171290b65e11f6a45aeeed15af
      
https://github.com/qemu/qemu/commit/4dd6517e369828171290b65e11f6a45aeeed15af
  Author: Peter Maydell <address@hidden>
  Date:   2020-03-19 (Thu, 19 Mar 2020)

  Changed paths:
    M hw/core/cpu.c
    M hw/core/machine.c
    M hw/i386/pc.c
    M hw/i386/x86.c
    M include/hw/boards.h
    M include/hw/core/cpu.h
    M include/hw/i386/topology.h
    M include/hw/i386/x86.h
    A scripts/coccinelle/cpu-reset.cocci
    M softmmu/vl.c
    M target/alpha/cpu-qom.h
    M target/arm/cpu-qom.h
    M target/arm/cpu.c
    M target/cris/cpu-qom.h
    M target/cris/cpu.c
    M target/hppa/cpu-qom.h
    M target/i386/cpu-qom.h
    M target/i386/cpu.c
    M target/i386/cpu.h
    M target/lm32/cpu-qom.h
    M target/lm32/cpu.c
    M target/m68k/cpu-qom.h
    M target/m68k/cpu.c
    M target/microblaze/cpu-qom.h
    M target/microblaze/cpu.c
    M target/mips/cpu-qom.h
    M target/mips/cpu.c
    M target/moxie/cpu.c
    M target/moxie/cpu.h
    M target/nios2/cpu.c
    M target/nios2/cpu.h
    M target/openrisc/cpu.c
    M target/openrisc/cpu.h
    M target/ppc/cpu-qom.h
    M target/ppc/translate_init.inc.c
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/s390x/cpu-qom.h
    M target/s390x/cpu.c
    M target/sh4/cpu-qom.h
    M target/sh4/cpu.c
    M target/sparc/cpu-qom.h
    M target/sparc/cpu.c
    M target/tilegx/cpu.c
    M target/tilegx/cpu.h
    M target/tricore/cpu-qom.h
    M target/tricore/cpu.c
    M target/xtensa/cpu-qom.h
    M target/xtensa/cpu.c
    M tests/test-x86-cpuid.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/ehabkost/tags/x86-and-machine-pull-request' into staging

x86 and machine queue for 5.0 soft freeze

Bug fixes:
* memory encryption: Disable mem merge
  (Dr. David Alan Gilbert)

Features:
* New EPYC CPU definitions (Babu Moger)
* Denventon-v2 CPU model (Tao Xu)
* New 'note' field on versioned CPU models (Tao Xu)

Cleanups:
* x86 CPU topology cleanups (Babu Moger)
* cpu: Use DeviceClass reset instead of a special CPUClass reset
  (Peter Maydell)

# gpg: Signature made Wed 18 Mar 2020 01:16:43 GMT
# gpg:                using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Eduardo Habkost <address@hidden>" [full]
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/x86-and-machine-pull-request:
  hw/i386: Rename apicid_from_topo_ids to x86_apicid_from_topo_ids
  hw/i386: Update structures to save the number of nodes per package
  hw/i386: Remove unnecessary initialization in x86_cpu_new
  machine: Add SMP Sockets in CpuTopology
  hw/i386: Consolidate topology functions
  hw/i386: Introduce X86CPUTopoInfo to contain topology info
  cpu: Use DeviceClass reset instead of a special CPUClass reset
  machine/memory encryption: Disable mem merge
  hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs
  i386: Add 2nd Generation AMD EPYC processors
  i386: Add missing cpu feature bits in EPYC model
  target/i386: Add new property note to versioned CPU models
  target/i386: Add Denverton-v2 (no MPX) CPU model

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/a1ba62a0f304...4dd6517e3698
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