[Qemu-commits] [qemu/qemu] 2a6332: target-arm: fix write helper for TLBI ALLE1IS

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 2a6332d968297266dbabf9d33f959e3a5efdd0f9
      
https://github.com/qemu/qemu/commit/2a6332d968297266dbabf9d33f959e3a5efdd0f9
  Author: Sergey Fedorov <address@hidden>
  Date:   2015-07-06 (Mon, 06 Jul 2015)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: fix write helper for TLBI ALLE1IS

TLBI ALLE1IS is an operation that does invalidate TLB entries on all PEs
in the same Inner Sharable domain, not just on the current CPU. So we
must use tlbiall_is_write() here.

Signed-off-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a7ffaf5c96e26820edffa94eeac766fe60bfdd31
      
https://github.com/qemu/qemu/commit/a7ffaf5c96e26820edffa94eeac766fe60bfdd31
  Author: Johannes Schlatow <address@hidden>
  Date:   2015-07-06 (Mon, 06 Jul 2015)

  Changed paths:
    M hw/timer/cadence_ttc.c

  Log Message:
  -----------
  Fix interval interrupt of cadence ttc when timer is in decrement mode

The interval interrupt is not set if the timer is in decrement mode.
This is because x >=0 and x < interval after leaving the while-loop.

Signed-off-by: Johannes Schlatow <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 049e24a191c212d9468db84169197887f2c91586
      
https://github.com/qemu/qemu/commit/049e24a191c212d9468db84169197887f2c91586
  Author: Peter Maydell <address@hidden>
  Date:   2015-07-06 (Mon, 06 Jul 2015)

  Changed paths:
    M target-arm/helper.h
    M target-arm/op_helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.h

  Log Message:
  -----------
  target-arm: Split DISAS_YIELD from DISAS_WFE

Currently we use DISAS_WFE for both WFE and YIELD instructions.
This is functionally correct because at the moment both of them
are implemented as "yield this CPU back to the top level loop so
another CPU has a chance to run". However it's rather confusing
that YIELD ends up calling HELPER(wfe), and if we ever want to
implement real behaviour for WFE and SEV it's likely to trip us up.

Split out the yield codepath to use DISAS_YIELD and a new
HELPER(yield) function, and have HELPER(wfe) call HELPER(yield).

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: c87e5a61c2b3024116f52f7e68273f864ff7ab82
      
https://github.com/qemu/qemu/commit/c87e5a61c2b3024116f52f7e68273f864ff7ab82
  Author: Peter Maydell <address@hidden>
  Date:   2015-07-06 (Mon, 06 Jul 2015)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Implement YIELD insn to yield in ARM and Thumb translators

Implement the YIELD instruction in the ARM and Thumb translators to
actually yield control back to the top level loop rather than being
a simple no-op. (We already do this for A64.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden


  Commit: 12dc273e98e4e111880b25c12bf671dc8951b8e6
      
https://github.com/qemu/qemu/commit/12dc273e98e4e111880b25c12bf671dc8951b8e6
  Author: Peter Maydell <address@hidden>
  Date:   2015-07-06 (Mon, 06 Jul 2015)

  Changed paths:
    M hw/intc/arm_gic_common.c

  Log Message:
  -----------
  hw/intc/arm_gic_common.c: Reset all registers

The arm_gic_common reset function was missing reset code for
several of the GIC's state fields:
 * bpr[]
 * abpr[]
 * priority1[]
 * priority2[]
 * sgi_pending[]
 * irq_target[] (SMP configurations only)

These probably went unnoticed because most guests will either
never touch them, or will write to them in the process of
configuring the GIC before enabling interrupts.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: 8a52340cbaf60d4dd0a78bbfe12632639fe3da6d
      
https://github.com/qemu/qemu/commit/8a52340cbaf60d4dd0a78bbfe12632639fe3da6d
  Author: Dmitry Osipenko <address@hidden>
  Date:   2015-07-06 (Mon, 06 Jul 2015)

  Changed paths:
    M hw/timer/arm_mptimer.c

  Log Message:
  -----------
  arm_mptimer: Fix timer shutdown and mode change

The running timer can't be stopped because timer control code just
doesn't handle disabling the timer. Fix it by deleting the timer if
the enable bit is cleared.

The timer won't start periodic ticking if a ONE-SHOT -> PERIODIC mode
change happens after a one-shot tick was completed. Fix it by
re-starting ticking if the timer isn't ticking right now.

To avoid code churning, these two fixes are squashed in one commit.

Signed-off-by: Dmitry Osipenko <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 257621a9566054472d1d55a819880d0f9da02bda
      
https://github.com/qemu/qemu/commit/257621a9566054472d1d55a819880d0f9da02bda
  Author: Dmitry Osipenko <address@hidden>
  Date:   2015-07-06 (Mon, 06 Jul 2015)

  Changed paths:
    M hw/timer/arm_mptimer.c

  Log Message:
  -----------
  arm_mptimer: Respect IT bit state

The timer should fire the interrupt only if the IT (interrupt enable) bit
state of the control register is enabled.

Signed-off-by: Dmitry Osipenko <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 261ccf426a6df854ba398be92413476919dd67f9
      
https://github.com/qemu/qemu/commit/261ccf426a6df854ba398be92413476919dd67f9
  Author: Peter Maydell <address@hidden>
  Date:   2015-07-06 (Mon, 06 Jul 2015)

  Changed paths:
    M hw/intc/arm_gic_common.c
    M hw/timer/arm_mptimer.c
    M hw/timer/cadence_ttc.c
    M target-arm/helper.c
    M target-arm/helper.h
    M target-arm/op_helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.c
    M target-arm/translate.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150706' 
into staging

target-arm queue:
 * TLBI ALLEI1IS should operate on all CPUs, not just this one
 * Fix interval interrupt of cadence ttc in decrement mode
 * Implement YIELD insn to yield in ARM and Thumb translators
 * ARM GIC: reset all registers
 * arm_mptimer: fix timer shutdown and mode change
 * arm_mptimer: respect IT bit state

# gpg: Signature made Mon Jul  6 10:58:27 2015 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20150706:
  arm_mptimer: Respect IT bit state
  arm_mptimer: Fix timer shutdown and mode change
  hw/intc/arm_gic_common.c: Reset all registers
  target-arm: Implement YIELD insn to yield in ARM and Thumb translators
  target-arm: Split DISAS_YIELD from DISAS_WFE
  Fix interval interrupt of cadence ttc when timer is in decrement mode
  target-arm: fix write helper for TLBI ALLE1IS

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/f50a1640fb82...261ccf426a6d