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[PATCH 06/33] hw/cpu/arm: Rename 'busdev' -> 'gicsbd' in a15mp_priv_real
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 06/33] hw/cpu/arm: Rename 'busdev' -> 'gicsbd' in a15mp_priv_realize() |
Date: |
Tue, 12 Dec 2023 17:29:06 +0100 |
'busdev' is the internal GIC as SysBus device.
Since we already have a 'gicdev' variable for the GIC as QDev,
rename 'busdev' as 'gicsbd' to make it clear we access the IRQ
lines from the GIC.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/cpu/a15mpcore.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index bfd8aa5644..a40f142128 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -51,7 +51,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
A15MPPrivState *s = A15MPCORE_PRIV(dev);
DeviceState *gicdev;
- SysBusDevice *busdev;
+ SysBusDevice *gicsbd;
int i;
bool has_el3;
bool has_el2 = false;
@@ -78,10 +78,10 @@ static void a15mp_priv_realize(DeviceState *dev, Error
**errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) {
return;
}
- busdev = SYS_BUS_DEVICE(&s->gic);
+ gicsbd = SYS_BUS_DEVICE(&s->gic);
/* Pass through outbound IRQ lines from the GIC */
- sysbus_pass_irq(sbd, busdev);
+ sysbus_pass_irq(sbd, gicsbd);
/* Pass through inbound GPIO lines to the GIC */
qdev_init_gpio_in(dev, a15mp_priv_set_irq, s->num_irq - 32);
@@ -126,17 +126,17 @@ static void a15mp_priv_realize(DeviceState *dev, Error
**errp)
* 0x6000-0x7fff -- GIC virtual CPU interface
*/
memory_region_add_subregion(&s->container, 0x1000,
- sysbus_mmio_get_region(busdev, 0));
+ sysbus_mmio_get_region(gicsbd, 0));
memory_region_add_subregion(&s->container, 0x2000,
- sysbus_mmio_get_region(busdev, 1));
+ sysbus_mmio_get_region(gicsbd, 1));
if (has_el2) {
memory_region_add_subregion(&s->container, 0x4000,
- sysbus_mmio_get_region(busdev, 2));
+ sysbus_mmio_get_region(gicsbd, 2));
memory_region_add_subregion(&s->container, 0x6000,
- sysbus_mmio_get_region(busdev, 3));
+ sysbus_mmio_get_region(gicsbd, 3));
for (i = 0; i < s->num_cpu; i++) {
hwaddr base = 0x5000 + i * 0x200;
- MemoryRegion *mr = sysbus_mmio_get_region(busdev,
+ MemoryRegion *mr = sysbus_mmio_get_region(gicsbd,
4 + s->num_cpu + i);
memory_region_add_subregion(&s->container, base, mr);
}
--
2.41.0
- [PATCH 00/33] hw/cpu/arm: Remove one use of qemu_get_cpu() in A7/A15 MPCore priv, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 01/33] hw/arm/boot: Propagate vCPU to arm_load_dtb(), Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 02/33] hw/arm/fsl-imx6: Add a local 'gic' variable, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 03/33] hw/arm/fsl-imx6ul: Add a local 'gic' variable, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 04/33] hw/arm/fsl-imx7: Add a local 'gic' variable, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 05/33] hw/cpu: Remove dead Kconfig, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 06/33] hw/cpu/arm: Rename 'busdev' -> 'gicsbd' in a15mp_priv_realize(),
Philippe Mathieu-Daudé <=
- [PATCH 07/33] hw/cpu/arm: Alias 'num-cpu' property on TYPE_REALVIEW_MPCORE, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 08/33] hw/cpu/arm: Declare CPU QOM types using DEFINE_TYPES() macro, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 09/33] hw/cpu/arm: Merge {a9mpcore.h, a15mpcore.h} as cortex_mpcore.h, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 10/33] hw/cpu/arm: Introduce abstract CORTEX_MPCORE_PRIV QOM type, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 11/33] hw/cpu/arm: Have A9MPCORE/A15MPCORE inheritate common CORTEX_MPCORE_PRIV, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 12/33] hw/cpu/arm: Create MPCore container in QOM parent, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 13/33] hw/cpu/arm: Handle 'num_cores' property once in MPCore parent, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 14/33] hw/cpu/arm: Handle 'has_el2/3' properties once in MPCore parent, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 15/33] hw/cpu/arm: Handle 'gic-irq' property once in MPCore parent, Philippe Mathieu-Daudé, 2023/12/12
- [PATCH 16/33] hw/cpu/arm: Handle GIC once in MPCore parent, Philippe Mathieu-Daudé, 2023/12/12