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[PATCH v2 07/15] target/arm: Pass an ARMSecuritySpace to arm_is_el2_enab
From: |
Peter Maydell |
Subject: |
[PATCH v2 07/15] target/arm: Pass an ARMSecuritySpace to arm_is_el2_enabled_secstate() |
Date: |
Mon, 7 Aug 2023 15:15:06 +0100 |
Pass an ARMSecuritySpace instead of a bool secure to
arm_is_el2_enabled_secstate(). This doesn't change behaviour.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 13 ++++++++-----
target/arm/helper.c | 2 +-
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index bcd65a63ca0..02bc8f0e8e0 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2504,17 +2504,19 @@ static inline bool arm_is_secure(CPUARMState *env)
/*
* Return true if the current security state has AArch64 EL2 or AArch32 Hyp.
- * This corresponds to the pseudocode EL2Enabled()
+ * This corresponds to the pseudocode EL2Enabled().
*/
-static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure)
+static inline bool arm_is_el2_enabled_secstate(CPUARMState *env,
+ ARMSecuritySpace space)
{
+ assert(space != ARMSS_Root);
return arm_feature(env, ARM_FEATURE_EL2)
- && (!secure || (env->cp15.scr_el3 & SCR_EEL2));
+ && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2));
}
static inline bool arm_is_el2_enabled(CPUARMState *env)
{
- return arm_is_el2_enabled_secstate(env, arm_is_secure_below_el3(env));
+ return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env));
}
#else
@@ -2538,7 +2540,8 @@ static inline bool arm_is_secure(CPUARMState *env)
return false;
}
-static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure)
+static inline bool arm_is_el2_enabled_secstate(CPUARMState *env,
+ ARMSecuritySpace space)
{
return false;
}
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 9862bc73b52..8290ca0aaad 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5778,7 +5778,7 @@ uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env,
ARMSecuritySpace space)
assert(space != ARMSS_Root);
- if (!arm_is_el2_enabled_secstate(env, arm_space_is_secure(space))) {
+ if (!arm_is_el2_enabled_secstate(env, space)) {
/*
* "This register has no effect if EL2 is not enabled in the
* current Security state". This is ARMv8.4-SecEL2 speak for
--
2.34.1
- [PATCH v2 02/15] target/arm/ptw: Don't report GPC faults on stage 1 ptw as stage2 faults, (continued)
- [PATCH v2 02/15] target/arm/ptw: Don't report GPC faults on stage 1 ptw as stage2 faults, Peter Maydell, 2023/08/07
- [PATCH v2 01/15] target/arm/ptw: Don't set fi->s1ptw for UnsuppAtomicUpdate fault, Peter Maydell, 2023/08/07
- [PATCH v2 06/15] target/arm/ptw: Pass an ARMSecuritySpace to arm_hcr_el2_eff_secstate(), Peter Maydell, 2023/08/07
- [PATCH v2 08/15] target/arm/ptw: Only fold in NSTable bit effects in Secure state, Peter Maydell, 2023/08/07
- [PATCH v2 09/15] target/arm/ptw: Remove last uses of ptw->in_secure, Peter Maydell, 2023/08/07
- [PATCH v2 03/15] target/arm/ptw: Set s1ns bit in fault info more consistently, Peter Maydell, 2023/08/07
- [PATCH v2 05/15] target/arm/ptw: Pass ARMSecurityState to regime_translation_disabled(), Peter Maydell, 2023/08/07
- [PATCH v2 11/15] target/arm/ptw: Drop S1Translate::out_secure, Peter Maydell, 2023/08/07
- [PATCH v2 04/15] target/arm/ptw: Pass ptw into get_phys_addr_pmsa*() and get_phys_addr_disabled(), Peter Maydell, 2023/08/07
- [PATCH v2 07/15] target/arm: Pass an ARMSecuritySpace to arm_is_el2_enabled_secstate(),
Peter Maydell <=
- [PATCH v2 14/15] target/arm/ptw: Report stage 2 fault level for stage 2 faults on stage 1 ptw, Peter Maydell, 2023/08/07
- [PATCH v2 13/15] target/arm/ptw: Check for block descriptors at invalid levels, Peter Maydell, 2023/08/07
- [PATCH v2 12/15] target/arm/ptw: Set attributes correctly for MMU disabled data accesses, Peter Maydell, 2023/08/07
- [PATCH v2 10/15] target/arm/ptw: Remove S1Translate::in_secure, Peter Maydell, 2023/08/07
- [PATCH v2 15/15] target/arm: Adjust PAR_EL1.SH for Device and Normal-NC memory types, Peter Maydell, 2023/08/07