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[PATCH v2 15/15] target/arm: Adjust PAR_EL1.SH for Device and Normal-NC
From: |
Peter Maydell |
Subject: |
[PATCH v2 15/15] target/arm: Adjust PAR_EL1.SH for Device and Normal-NC memory types |
Date: |
Mon, 7 Aug 2023 15:15:14 +0100 |
The PAR_EL1.SH field documents that for the cases of:
* Device memory
* Normal memory with both Inner and Outer Non-Cacheable
the field should be 0b10 rather than whatever was in the
translation table descriptor field. (In the pseudocode this
is handled by PAREncodeShareability().) Perform this
adjustment when assembling a PAR value.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8290ca0aaad..da5db6d3ff6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3342,6 +3342,19 @@ static CPAccessResult ats_access(CPUARMState *env, const
ARMCPRegInfo *ri,
}
#ifdef CONFIG_TCG
+static int par_el1_shareability(GetPhysAddrResult *res)
+{
+ /*
+ * The PAR_EL1.SH field must be 0b10 for Device or Normal-NC
+ * memory -- see pseudocode PAREncodeShareability().
+ */
+ if (((res->cacheattrs.attrs & 0xf0) == 0) ||
+ res->cacheattrs.attrs == 0x44 || res->cacheattrs.attrs == 0x40) {
+ return 2;
+ }
+ return res->cacheattrs.shareability;
+}
+
static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
bool is_secure)
@@ -3470,7 +3483,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t
value,
par64 |= (1 << 9); /* NS */
}
par64 |= (uint64_t)res.cacheattrs.attrs << 56; /* ATTR */
- par64 |= res.cacheattrs.shareability << 7; /* SH */
+ par64 |= par_el1_shareability(&res) << 7; /* SH */
} else {
uint32_t fsr = arm_fi_to_lfsc(&fi);
--
2.34.1
- [PATCH v2 03/15] target/arm/ptw: Set s1ns bit in fault info more consistently, (continued)
- [PATCH v2 03/15] target/arm/ptw: Set s1ns bit in fault info more consistently, Peter Maydell, 2023/08/07
- [PATCH v2 05/15] target/arm/ptw: Pass ARMSecurityState to regime_translation_disabled(), Peter Maydell, 2023/08/07
- [PATCH v2 11/15] target/arm/ptw: Drop S1Translate::out_secure, Peter Maydell, 2023/08/07
- [PATCH v2 04/15] target/arm/ptw: Pass ptw into get_phys_addr_pmsa*() and get_phys_addr_disabled(), Peter Maydell, 2023/08/07
- [PATCH v2 07/15] target/arm: Pass an ARMSecuritySpace to arm_is_el2_enabled_secstate(), Peter Maydell, 2023/08/07
- [PATCH v2 14/15] target/arm/ptw: Report stage 2 fault level for stage 2 faults on stage 1 ptw, Peter Maydell, 2023/08/07
- [PATCH v2 13/15] target/arm/ptw: Check for block descriptors at invalid levels, Peter Maydell, 2023/08/07
- [PATCH v2 12/15] target/arm/ptw: Set attributes correctly for MMU disabled data accesses, Peter Maydell, 2023/08/07
- [PATCH v2 10/15] target/arm/ptw: Remove S1Translate::in_secure, Peter Maydell, 2023/08/07
- [PATCH v2 15/15] target/arm: Adjust PAR_EL1.SH for Device and Normal-NC memory types,
Peter Maydell <=