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[PATCH v2 11/15] target/arm/ptw: Drop S1Translate::out_secure
From: |
Peter Maydell |
Subject: |
[PATCH v2 11/15] target/arm/ptw: Drop S1Translate::out_secure |
Date: |
Mon, 7 Aug 2023 15:15:10 +0100 |
We only use S1Translate::out_secure in two places, where we are
setting up MemTxAttrs for a page table load. We can use
arm_space_is_secure(ptw->out_space) instead, which guarantees
that we're setting the MemTxAttrs secure and space fields
consistently, and allows us to drop the out_secure field in
S1Translate entirely.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/ptw.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 78bc679deef..312ccabe92e 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -63,7 +63,6 @@ typedef struct S1Translate {
* Stage 2 is indicated by in_mmu_idx set to ARMMMUIdx_Stage2{,_S}.
*/
bool in_s1_is_el0;
- bool out_secure;
bool out_rw;
bool out_be;
ARMSecuritySpace out_space;
@@ -553,7 +552,6 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate
*ptw,
pte_attrs = s2.cacheattrs.attrs;
ptw->out_host = NULL;
ptw->out_rw = false;
- ptw->out_secure = s2.f.attrs.secure;
ptw->out_space = s2.f.attrs.space;
} else {
#ifdef CONFIG_TCG
@@ -572,7 +570,6 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate
*ptw,
ptw->out_phys = full->phys_addr | (addr & ~TARGET_PAGE_MASK);
ptw->out_rw = full->prot & PAGE_WRITE;
pte_attrs = full->pte_attrs;
- ptw->out_secure = full->attrs.secure;
ptw->out_space = full->attrs.space;
#else
g_assert_not_reached();
@@ -630,8 +627,8 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, S1Translate
*ptw,
} else {
/* Page tables are in MMIO. */
MemTxAttrs attrs = {
- .secure = ptw->out_secure,
.space = ptw->out_space,
+ .secure = arm_space_is_secure(ptw->out_space),
};
AddressSpace *as = arm_addressspace(cs, attrs);
MemTxResult result = MEMTX_OK;
@@ -676,8 +673,8 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, S1Translate
*ptw,
} else {
/* Page tables are in MMIO. */
MemTxAttrs attrs = {
- .secure = ptw->out_secure,
.space = ptw->out_space,
+ .secure = arm_space_is_secure(ptw->out_space),
};
AddressSpace *as = arm_addressspace(cs, attrs);
MemTxResult result = MEMTX_OK;
--
2.34.1
- [PATCH v2 00/15] target/arm/ptw: Cleanups and a few bugfixes, Peter Maydell, 2023/08/07
- [PATCH v2 02/15] target/arm/ptw: Don't report GPC faults on stage 1 ptw as stage2 faults, Peter Maydell, 2023/08/07
- [PATCH v2 01/15] target/arm/ptw: Don't set fi->s1ptw for UnsuppAtomicUpdate fault, Peter Maydell, 2023/08/07
- [PATCH v2 06/15] target/arm/ptw: Pass an ARMSecuritySpace to arm_hcr_el2_eff_secstate(), Peter Maydell, 2023/08/07
- [PATCH v2 08/15] target/arm/ptw: Only fold in NSTable bit effects in Secure state, Peter Maydell, 2023/08/07
- [PATCH v2 09/15] target/arm/ptw: Remove last uses of ptw->in_secure, Peter Maydell, 2023/08/07
- [PATCH v2 03/15] target/arm/ptw: Set s1ns bit in fault info more consistently, Peter Maydell, 2023/08/07
- [PATCH v2 05/15] target/arm/ptw: Pass ARMSecurityState to regime_translation_disabled(), Peter Maydell, 2023/08/07
- [PATCH v2 11/15] target/arm/ptw: Drop S1Translate::out_secure,
Peter Maydell <=
- [PATCH v2 04/15] target/arm/ptw: Pass ptw into get_phys_addr_pmsa*() and get_phys_addr_disabled(), Peter Maydell, 2023/08/07
- [PATCH v2 07/15] target/arm: Pass an ARMSecuritySpace to arm_is_el2_enabled_secstate(), Peter Maydell, 2023/08/07
- [PATCH v2 14/15] target/arm/ptw: Report stage 2 fault level for stage 2 faults on stage 1 ptw, Peter Maydell, 2023/08/07
- [PATCH v2 13/15] target/arm/ptw: Check for block descriptors at invalid levels, Peter Maydell, 2023/08/07
- [PATCH v2 12/15] target/arm/ptw: Set attributes correctly for MMU disabled data accesses, Peter Maydell, 2023/08/07
- [PATCH v2 10/15] target/arm/ptw: Remove S1Translate::in_secure, Peter Maydell, 2023/08/07
- [PATCH v2 15/15] target/arm: Adjust PAR_EL1.SH for Device and Normal-NC memory types, Peter Maydell, 2023/08/07