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[PATCH v2 24/33] accel/tcg: Split log_cpu_exec into inline and slow path
From: |
Richard Henderson |
Subject: |
[PATCH v2 24/33] accel/tcg: Split log_cpu_exec into inline and slow path |
Date: |
Tue, 16 Aug 2022 15:33:51 -0500 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/cpu-exec.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index f7c82a8f2c..d758396bcd 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -283,12 +283,11 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu,
target_ulong pc,
return tb;
}
-static inline void log_cpu_exec(target_ulong pc, CPUState *cpu,
- const TranslationBlock *tb)
+static void log_cpu_exec1(CPUState *cpu, const TranslationBlock *tb)
{
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC))
- && qemu_log_in_addr_range(pc)) {
+ target_ulong pc = tb_pc_log(tb);
+ if (qemu_log_in_addr_range(pc)) {
qemu_log_mask(CPU_LOG_EXEC,
"Trace %d: %p [" TARGET_FMT_lx
"/" TARGET_FMT_lx "/%08x/%08x] %s\n",
@@ -315,6 +314,13 @@ static inline void log_cpu_exec(target_ulong pc, CPUState
*cpu,
}
}
+static inline void log_cpu_exec(CPUState *cpu, const TranslationBlock *tb)
+{
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC))) {
+ log_cpu_exec1(cpu, tb);
+ }
+}
+
static bool check_for_breakpoints(CPUState *cpu, target_ulong pc,
uint32_t *cflags)
{
@@ -412,7 +418,7 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env)
return tcg_code_gen_epilogue;
}
- log_cpu_exec(pc, cpu, tb);
+ log_cpu_exec(cpu, tb);
return tb->tc.ptr;
}
@@ -435,7 +441,7 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int
*tb_exit)
TranslationBlock *last_tb;
const void *tb_ptr = itb->tc.ptr;
- log_cpu_exec(tb_pc_log(itb), cpu, itb);
+ log_cpu_exec(cpu, itb);
qemu_thread_jit_execute();
ret = tcg_qemu_tb_exec(env, tb_ptr);
--
2.34.1
- [PATCH v2 13/33] accel/tcg: Unlock mmap_lock after longjmp, (continued)
- [PATCH v2 13/33] accel/tcg: Unlock mmap_lock after longjmp, Richard Henderson, 2022/08/16
- [PATCH v2 19/33] accel/tcg: Use DisasContextBase in plugin_gen_tb_start, Richard Henderson, 2022/08/16
- [PATCH v2 21/33] include/hw/core: Create struct CPUJumpCache, Richard Henderson, 2022/08/16
- [PATCH v2 15/33] accel/tcg: Introduce is_same_page(), Richard Henderson, 2022/08/16
- [PATCH v2 17/33] accel/tcg: Add pc and host_pc params to gen_intermediate_code, Richard Henderson, 2022/08/16
- [PATCH v2 07/33] accel/tcg: Use bool for page_find_alloc, Richard Henderson, 2022/08/16
- [PATCH v2 20/33] accel/tcg: Do not align tb->page_addr[0], Richard Henderson, 2022/08/16
- [PATCH v2 12/33] accel/tcg: Add nofault parameter to get_page_addr_code_hostp, Richard Henderson, 2022/08/16
- [PATCH v2 18/33] accel/tcg: Add fast path for translator_ld*, Richard Henderson, 2022/08/16
- [PATCH v2 10/33] accel/tcg: Properly implement get_page_addr_code for user-only, Richard Henderson, 2022/08/16
- [PATCH v2 24/33] accel/tcg: Split log_cpu_exec into inline and slow path,
Richard Henderson <=
- [PATCH v2 26/33] target/arm: Change gen_goto_tb to work on displacements, Richard Henderson, 2022/08/16
- [PATCH v2 25/33] target/arm: Introduce curr_insn_len, Richard Henderson, 2022/08/16
- [PATCH v2 27/33] target/arm: Change gen_*set_pc_im to gen_*update_pc, Richard Henderson, 2022/08/16
- [PATCH v2 23/33] accel/tcg: Introduce TARGET_TB_PCREL, Richard Henderson, 2022/08/16
- [PATCH v2 32/33] target/arm: Introduce gen_pc_plus_diff for aarch32, Richard Henderson, 2022/08/16
- [PATCH v2 28/33] target/arm: Change gen_exception_insn* to work on displacements, Richard Henderson, 2022/08/16
- [PATCH v2 33/33] target/arm: Enable TARGET_TB_PCREL, Richard Henderson, 2022/08/16
- [PATCH v2 30/33] target/arm: Change gen_jmp* to work on displacements, Richard Henderson, 2022/08/16
- [PATCH v2 22/33] accel/tcg: Introduce tb_pc and tb_pc_log, Richard Henderson, 2022/08/16