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[PATCH v2 12/33] accel/tcg: Add nofault parameter to get_page_addr_code_
From: |
Richard Henderson |
Subject: |
[PATCH v2 12/33] accel/tcg: Add nofault parameter to get_page_addr_code_hostp |
Date: |
Tue, 16 Aug 2022 15:33:39 -0500 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/exec-all.h | 10 +++++-----
accel/tcg/cputlb.c | 8 ++++----
accel/tcg/plugin-gen.c | 4 ++--
accel/tcg/user-exec.c | 4 ++--
4 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 9f35e3b7a9..7a6dc44d86 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -599,6 +599,8 @@ struct MemoryRegionSection *iotlb_to_section(CPUState *cpu,
* get_page_addr_code_hostp()
* @env: CPUArchState
* @addr: guest virtual address of guest code
+ * @nofault: do not raise an exception
+ * @hostp: output for host pointer
*
* See get_page_addr_code() (full-system version) for documentation on the
* return value.
@@ -607,10 +609,10 @@ struct MemoryRegionSection *iotlb_to_section(CPUState
*cpu,
* If the return value is -1, sets *@hostp to NULL. Otherwise, sets *@hostp
* to the host address where @addr's content is kept.
*
- * Note: this function can trigger an exception.
+ * Note: Unless @nofault, this function can trigger an exception.
*/
tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
- void **hostp);
+ bool nofault, void **hostp);
/**
* get_page_addr_code()
@@ -620,13 +622,11 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState
*env, target_ulong addr,
* If we cannot translate and execute from the entire RAM page, or if
* the region is not backed by RAM, returns -1. Otherwise, returns the
* ram_addr_t corresponding to the guest code at @addr.
- *
- * Note: this function can trigger an exception.
*/
static inline tb_page_addr_t get_page_addr_code(CPUArchState *env,
target_ulong addr)
{
- return get_page_addr_code_hostp(env, addr, NULL);
+ return get_page_addr_code_hostp(env, addr, true, NULL);
}
#if defined(CONFIG_USER_ONLY)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 2dc2affa12..ae7b40dd51 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1644,16 +1644,16 @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
* of RAM. This will force us to execute by loading and translating
* one insn at a time, without caching.
*
- * NOTE: This function will trigger an exception if the page is
- * not executable.
+ * NOTE: Unless @nofault, this function will trigger an exception
+ * if the page is not executable.
*/
tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
- void **hostp)
+ bool nofault, void **hostp)
{
void *p;
(void)probe_access_internal(env, addr, 1, MMU_INST_FETCH,
- cpu_mmu_index(env, true), true, &p, 0);
+ cpu_mmu_index(env, true), nofault, &p, 0);
if (p == NULL) {
return -1;
}
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index 3d0b101e34..8377c15383 100644
--- a/accel/tcg/plugin-gen.c
+++ b/accel/tcg/plugin-gen.c
@@ -872,7 +872,7 @@ bool plugin_gen_tb_start(CPUState *cpu, const
TranslationBlock *tb, bool mem_onl
ptb->vaddr = tb->pc;
ptb->vaddr2 = -1;
- get_page_addr_code_hostp(cpu->env_ptr, tb->pc, &ptb->haddr1);
+ get_page_addr_code_hostp(cpu->env_ptr, tb->pc, true, &ptb->haddr1);
ptb->haddr2 = NULL;
ptb->mem_only = mem_only;
@@ -902,7 +902,7 @@ void plugin_gen_insn_start(CPUState *cpu, const
DisasContextBase *db)
unlikely((db->pc_next & TARGET_PAGE_MASK) !=
(db->pc_first & TARGET_PAGE_MASK))) {
get_page_addr_code_hostp(cpu->env_ptr, db->pc_next,
- &ptb->haddr2);
+ true, &ptb->haddr2);
ptb->vaddr2 = db->pc_next;
}
if (likely(ptb->vaddr2 == -1)) {
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index a20234fb02..1b3403a064 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -200,11 +200,11 @@ void *probe_access(CPUArchState *env, target_ulong addr,
int size,
}
tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
- void **hostp)
+ bool nofault, void **hostp)
{
int flags;
- flags = probe_access_internal(env, addr, 1, MMU_INST_FETCH, true, 0);
+ flags = probe_access_internal(env, addr, 1, MMU_INST_FETCH, nofault, 0);
if (unlikely(flags)) {
return -1;
}
--
2.34.1
- [PATCH v2 08/33] accel/tcg: Make tb_htable_lookup static, (continued)
- [PATCH v2 08/33] accel/tcg: Make tb_htable_lookup static, Richard Henderson, 2022/08/16
- [PATCH v2 04/33] linux-user: Honor PT_GNU_STACK, Richard Henderson, 2022/08/16
- [PATCH v2 14/33] accel/tcg: Raise PROT_EXEC exception early, Richard Henderson, 2022/08/16
- [PATCH v2 13/33] accel/tcg: Unlock mmap_lock after longjmp, Richard Henderson, 2022/08/16
- [PATCH v2 19/33] accel/tcg: Use DisasContextBase in plugin_gen_tb_start, Richard Henderson, 2022/08/16
- [PATCH v2 21/33] include/hw/core: Create struct CPUJumpCache, Richard Henderson, 2022/08/16
- [PATCH v2 15/33] accel/tcg: Introduce is_same_page(), Richard Henderson, 2022/08/16
- [PATCH v2 17/33] accel/tcg: Add pc and host_pc params to gen_intermediate_code, Richard Henderson, 2022/08/16
- [PATCH v2 07/33] accel/tcg: Use bool for page_find_alloc, Richard Henderson, 2022/08/16
- [PATCH v2 20/33] accel/tcg: Do not align tb->page_addr[0], Richard Henderson, 2022/08/16
- [PATCH v2 12/33] accel/tcg: Add nofault parameter to get_page_addr_code_hostp,
Richard Henderson <=
- [PATCH v2 18/33] accel/tcg: Add fast path for translator_ld*, Richard Henderson, 2022/08/16
- [PATCH v2 10/33] accel/tcg: Properly implement get_page_addr_code for user-only, Richard Henderson, 2022/08/16
- [PATCH v2 24/33] accel/tcg: Split log_cpu_exec into inline and slow path, Richard Henderson, 2022/08/16
- [PATCH v2 26/33] target/arm: Change gen_goto_tb to work on displacements, Richard Henderson, 2022/08/16
- [PATCH v2 25/33] target/arm: Introduce curr_insn_len, Richard Henderson, 2022/08/16
- [PATCH v2 27/33] target/arm: Change gen_*set_pc_im to gen_*update_pc, Richard Henderson, 2022/08/16
- [PATCH v2 23/33] accel/tcg: Introduce TARGET_TB_PCREL, Richard Henderson, 2022/08/16
- [PATCH v2 32/33] target/arm: Introduce gen_pc_plus_diff for aarch32, Richard Henderson, 2022/08/16
- [PATCH v2 28/33] target/arm: Change gen_exception_insn* to work on displacements, Richard Henderson, 2022/08/16
- [PATCH v2 33/33] target/arm: Enable TARGET_TB_PCREL, Richard Henderson, 2022/08/16