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[PULL 13/19] docs: aspeed: Minor updates
From: |
Cédric Le Goater |
Subject: |
[PULL 13/19] docs: aspeed: Minor updates |
Date: |
Wed, 13 Jul 2022 09:52:49 +0200 |
Some more controllers have been modeled recently. Reflect that in the
list of supported devices. New machines were also added.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20220706172131.809255-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
docs/system/arm/aspeed.rst | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 445095690c04..6c5b05128ea8 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -31,7 +31,10 @@ AST2600 SoC based machines :
- ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC
- ``rainier-bmc`` IBM Rainier POWER10 BMC
- ``fuji-bmc`` Facebook Fuji BMC
+- ``bletchley-bmc`` Facebook Bletchley BMC
- ``fby35-bmc`` Facebook fby35 BMC
+- ``qcom-dc-scm-v1-bmc`` Qualcomm DC-SCM V1 BMC
+- ``qcom-firework-bmc`` Qualcomm Firework BMC
Supported devices
-----------------
@@ -40,7 +43,7 @@ Supported devices
* Interrupt Controller (VIC)
* Timer Controller
* RTC Controller
- * I2C Controller
+ * I2C Controller, including the new register interface of the AST2600
* System Control Unit (SCU)
* SRAM mapping
* X-DMA Controller (basic interface)
@@ -57,6 +60,10 @@ Supported devices
* LPC Peripheral Controller (a subset of subdevices are supported)
* Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA
* ADC
+ * Secure Boot Controller (AST2600)
+ * eMMC Boot Controller (dummy)
+ * PECI Controller (minimal)
+ * I3C Controller
Missing devices
@@ -68,12 +75,10 @@ Missing devices
* Super I/O Controller
* PCI-Express 1 Controller
* Graphic Display Controller
- * PECI Controller
* MCTP Controller
* Mailbox Controller
* Virtual UART
* eSPI Controller
- * I3C Controller
Boot options
------------
@@ -154,6 +159,8 @@ Supported devices
* LPC Peripheral Controller (a subset of subdevices are supported)
* Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA
* ADC
+ * Secure Boot Controller
+ * PECI Controller (minimal)
Missing devices
@@ -161,7 +168,6 @@ Missing devices
* PWM and Fan Controller
* Slave GPIO Controller
- * PECI Controller
* Mailbox Controller
* Virtual UART
* eSPI Controller
--
2.35.3
- [PULL 06/19] aspeed: Refactor UART init for multi-SoC machines, (continued)
- [PULL 06/19] aspeed: Refactor UART init for multi-SoC machines, Cédric Le Goater, 2022/07/13
- [PULL 07/19] aspeed: Make aspeed_board_init_flashes public, Cédric Le Goater, 2022/07/13
- [PULL 14/19] test/avocado/machine_aspeed.py: Add SDK tests, Cédric Le Goater, 2022/07/13
- [PULL 08/19] aspeed: Add fby35 skeleton, Cédric Le Goater, 2022/07/13
- [PULL 05/19] aspeed: Create SRAM name from first CPU index, Cédric Le Goater, 2022/07/13
- [PULL 11/19] aspeed: Add AST1030 (BIC) to fby35, Cédric Le Goater, 2022/07/13
- [PULL 15/19] hw: m25p80: Add Block Protect and Top Bottom bits for write protect, Cédric Le Goater, 2022/07/13
- [PULL 09/19] aspeed: Add AST2600 (BMC) to fby35, Cédric Le Goater, 2022/07/13
- [PULL 10/19] aspeed: fby35: Add a bootrom for the BMC, Cédric Le Goater, 2022/07/13
- [PULL 12/19] docs: aspeed: Add fby35 multi-SoC machine section, Cédric Le Goater, 2022/07/13
- [PULL 13/19] docs: aspeed: Minor updates,
Cédric Le Goater <=
- [PULL 16/19] hw: m25p80: add tests for BP and TB bit write protect, Cédric Le Goater, 2022/07/13
- [PULL 18/19] hw/gpio/aspeed: Don't let guests modify input pins, Cédric Le Goater, 2022/07/13
- [PULL 17/19] qtest/aspeed_gpio: Add input pin modification test, Cédric Le Goater, 2022/07/13
- [PULL 19/19] aspeed: Add fby35-bmc slot GPIO's, Cédric Le Goater, 2022/07/13
- Re: [PULL 00/19] aspeed queue, Peter Maydell, 2022/07/14