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[PATCH v5 09/31] target/arm: Move TBFLAG_ANY bits to the bottom
From: |
Richard Henderson |
Subject: |
[PATCH v5 09/31] target/arm: Move TBFLAG_ANY bits to the bottom |
Date: |
Mon, 19 Apr 2021 13:22:35 -0700 |
Now that other bits have been moved out of tb->flags,
there's no point in filling from the top.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 15104e1440..5e0131be1a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3405,15 +3405,15 @@ typedef ARMCPU ArchCPU;
*
* Unless otherwise noted, these bits are cached in env->hflags.
*/
-FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1)
-FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1)
-FIELD(TBFLAG_ANY, PSTATE__SS, 29, 1) /* Not cached. */
-FIELD(TBFLAG_ANY, BE_DATA, 28, 1)
-FIELD(TBFLAG_ANY, MMUIDX, 24, 4)
+FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1)
+FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1)
+FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */
+FIELD(TBFLAG_ANY, BE_DATA, 3, 1)
+FIELD(TBFLAG_ANY, MMUIDX, 4, 4)
/* Target EL if we take a floating-point-disabled exception */
-FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2)
+FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
/* For A-profile only, target EL for debug exceptions. */
-FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2)
+FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2)
/*
* Bit usage when in AArch32 state, both A- and M-profile.
--
2.25.1
- [PATCH v5 00/31] target/arm: enforce alignment, Richard Henderson, 2021/04/19
- [PATCH v5 01/31] target/arm: Fix decode of align in VLDST_single, Richard Henderson, 2021/04/19
- [PATCH v5 02/31] target/arm: Rename TBFLAG_A32, SCTLR_B, Richard Henderson, 2021/04/19
- [PATCH v5 03/31] target/arm: Rename TBFLAG_ANY, PSTATE_SS, Richard Henderson, 2021/04/19
- [PATCH v5 05/31] target/arm: Introduce CPUARMTBFlags, Richard Henderson, 2021/04/19
- [PATCH v5 04/31] target/arm: Add wrapper macros for accessing tbflags, Richard Henderson, 2021/04/19
- [PATCH v5 06/31] target/arm: Move mode specific TB flags to tb->cs_base, Richard Henderson, 2021/04/19
- [PATCH v5 07/31] target/arm: Use cpu_abort in assert_hflags_rebuild_correctly, Richard Henderson, 2021/04/19
- [PATCH v5 08/31] target/arm: Move TBFLAG_AM32 bits to the top, Richard Henderson, 2021/04/19
- [PATCH v5 09/31] target/arm: Move TBFLAG_ANY bits to the bottom,
Richard Henderson <=
- [PATCH v5 10/31] target/arm: Add ALIGN_MEM to TBFLAG_ANY, Richard Henderson, 2021/04/19
- [PATCH v5 12/31] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64, Richard Henderson, 2021/04/19
- [PATCH v5 13/31] target/arm: Fix SCTLR_B test for TCGv_i64 load/store, Richard Henderson, 2021/04/19
- [PATCH v5 14/31] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness, Richard Henderson, 2021/04/19
- [PATCH v5 11/31] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness, Richard Henderson, 2021/04/19
- [PATCH v5 15/31] target/arm: Enforce word alignment for LDRD/STRD, Richard Henderson, 2021/04/19
- [PATCH v5 17/31] target/arm: Enforce alignment for LDM/STM, Richard Henderson, 2021/04/19
- [PATCH v5 16/31] target/arm: Enforce alignment for LDA/LDAH/STL/STLH, Richard Henderson, 2021/04/19
- [PATCH v5 18/31] target/arm: Enforce alignment for RFE, Richard Henderson, 2021/04/19
- [PATCH v5 19/31] target/arm: Enforce alignment for SRS, Richard Henderson, 2021/04/19