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[PATCH v5 02/31] target/arm: Rename TBFLAG_A32, SCTLR_B
From: |
Richard Henderson |
Subject: |
[PATCH v5 02/31] target/arm: Rename TBFLAG_A32, SCTLR_B |
Date: |
Mon, 19 Apr 2021 13:22:28 -0700 |
We're about to rearrange the macro expansion surrounding tbflags,
and this field name will be expanded using the bit definition of
the same name, resulting in a token pasting error.
So SCTLR_B -> SCTLR__B in the 3 uses, and document it.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 2 +-
target/arm/helper.c | 2 +-
target/arm/translate.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 193a49ec7f..304e0a6af3 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3423,7 +3423,7 @@ FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */
*/
FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2)
FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. */
-FIELD(TBFLAG_A32, SCTLR_B, 15, 1)
+FIELD(TBFLAG_A32, SCTLR__B, 15, 1) /* Cannot overlap with SCTLR_B */
FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1)
/*
* Indicates whether cp register reads and writes by guest code should access
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d9220be7c5..556b9d4f0a 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -13003,7 +13003,7 @@ static uint32_t rebuild_hflags_common_32(CPUARMState
*env, int fp_el,
bool sctlr_b = arm_sctlr_b(env);
if (sctlr_b) {
- flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, 1);
+ flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR__B, 1);
}
if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) {
flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1);
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 7103da2d7a..0b56e060a5 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8879,7 +8879,7 @@ static void arm_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE;
dc->debug_target_el =
FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL);
- dc->sctlr_b = FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR_B);
+ dc->sctlr_b = FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR__B);
dc->hstr_active = FIELD_EX32(tb_flags, TBFLAG_A32, HSTR_ACTIVE);
dc->ns = FIELD_EX32(tb_flags, TBFLAG_A32, NS);
dc->vfp_enabled = FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN);
--
2.25.1
- [PATCH v5 00/31] target/arm: enforce alignment, Richard Henderson, 2021/04/19
- [PATCH v5 01/31] target/arm: Fix decode of align in VLDST_single, Richard Henderson, 2021/04/19
- [PATCH v5 02/31] target/arm: Rename TBFLAG_A32, SCTLR_B,
Richard Henderson <=
- [PATCH v5 03/31] target/arm: Rename TBFLAG_ANY, PSTATE_SS, Richard Henderson, 2021/04/19
- [PATCH v5 05/31] target/arm: Introduce CPUARMTBFlags, Richard Henderson, 2021/04/19
- [PATCH v5 04/31] target/arm: Add wrapper macros for accessing tbflags, Richard Henderson, 2021/04/19
- [PATCH v5 06/31] target/arm: Move mode specific TB flags to tb->cs_base, Richard Henderson, 2021/04/19
- [PATCH v5 07/31] target/arm: Use cpu_abort in assert_hflags_rebuild_correctly, Richard Henderson, 2021/04/19
- [PATCH v5 08/31] target/arm: Move TBFLAG_AM32 bits to the top, Richard Henderson, 2021/04/19
- [PATCH v5 09/31] target/arm: Move TBFLAG_ANY bits to the bottom, Richard Henderson, 2021/04/19
- [PATCH v5 10/31] target/arm: Add ALIGN_MEM to TBFLAG_ANY, Richard Henderson, 2021/04/19
- [PATCH v5 12/31] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64, Richard Henderson, 2021/04/19