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Re: [PATCH 09/10] target/arm: Implement FPSCR.LTPSIZE for M-profile LOB
From: |
Richard Henderson |
Subject: |
Re: [PATCH 09/10] target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension |
Date: |
Tue, 13 Oct 2020 13:06:21 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 10/12/20 8:37 AM, Peter Maydell wrote:
> @@ -198,8 +200,14 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t
> val)
> /*
> * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits
> * and also for the trapped-exception-handling bits IxE.
> + * From v8.1M with the low-overhead-loop extension bits
> + * [18:16] are used for LTPSIZE and (since we don't implement
> + * MVE) always read as 4 and ignore writes.
> */
> val &= 0xf7c0009f;
> + if (cpu_isar_feature(aa32_lob, cpu)) {
> + val |= 4 << 16;
> + }
> }
>
> vfp_set_fpscr_to_host(env, val);
> @@ -212,9 +220,18 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t
> val)
> * (which are stored in fp_status), and the other RES0 bits
> * in between, then we clear all of the low 16 bits.
> */
> - env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000;
> - env->vfp.vec_len = (val >> 16) & 7;
> - env->vfp.vec_stride = (val >> 20) & 3;
> + if (cpu_isar_feature(aa32_lob, cpu)) {
> + /*
> + * M-profile low-overhead-loop extension: [18:16] are LTPSIZE
> + * and we keep them in vfp.xregs[].
> + */
> + env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7cf0000;
> + } else {
> + /* Those bits might be the old-style short vector length/stride */
> + env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000;
> + env->vfp.vec_len = (val >> 16) & 7;
> + env->vfp.vec_stride = (val >> 20) & 3;
> + }
I think these two sets of masking are confusing.
Perhaps usefully rearranged as
if (!fp16) {
val &= ~fz16;
}
vfp_set_fpscr_to_host(env, val);
if (!m-profile) {
vec_len = extract32(val, 16, 3);
vec_stride = extract32(val, 20, 2);
}
val &= 0xf7c80000;
if (lob) {
val |= 4 << 16;
}
fpscr = val;
Which then obviates the next patch.
r~
- [PATCH 07/10] target/arm: Implement v8.1M low-overhead-loop instructions, (continued)
- [PATCH 07/10] target/arm: Implement v8.1M low-overhead-loop instructions, Peter Maydell, 2020/10/12
- Re: [PATCH 07/10] target/arm: Implement v8.1M low-overhead-loop instructions, Peter Maydell, 2020/10/12
- Re: [PATCH 07/10] target/arm: Implement v8.1M low-overhead-loop instructions, Richard Henderson, 2020/10/13
- Re: [PATCH 07/10] target/arm: Implement v8.1M low-overhead-loop instructions, Peter Maydell, 2020/10/13
- Re: [PATCH 07/10] target/arm: Implement v8.1M low-overhead-loop instructions, Richard Henderson, 2020/10/13
- Re: [PATCH 07/10] target/arm: Implement v8.1M low-overhead-loop instructions, Peter Maydell, 2020/10/13
- Re: [PATCH 07/10] target/arm: Implement v8.1M low-overhead-loop instructions, Richard Henderson, 2020/10/13
[PATCH 03/10] target/arm: Implement v8.1M conditional-select insns, Peter Maydell, 2020/10/12
[PATCH 09/10] target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension, Peter Maydell, 2020/10/12
[PATCH 05/10] target/arm: Don't allow BLX imm for M-profile, Peter Maydell, 2020/10/12
[PATCH 08/10] target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile, Peter Maydell, 2020/10/12
[PATCH 04/10] target/arm: Make the t32 insn[25:23]=111 group non-overlapping, Peter Maydell, 2020/10/12
[PATCH 06/10] target/arm: Implement v8.1M branch-future insns (as NOPs), Peter Maydell, 2020/10/12