[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 05/10] target/arm: Don't allow BLX imm for M-profile
From: |
Peter Maydell |
Subject: |
[PATCH 05/10] target/arm: Don't allow BLX imm for M-profile |
Date: |
Mon, 12 Oct 2020 16:37:41 +0100 |
The BLX immediate insn in the Thumb encoding always performs
a switch from Thumb to Arm state. This would be totally useless
in M-profile which has no Arm decoder, and so the instruction
does not exist at all there. Make the encoding UNDEF for M-profile.
(This part of the encoding space is used for the branch-future
and low-overhead-loop insns in v8.1M.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index a7923a31b56..0c35efb1014 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7880,6 +7880,14 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a)
{
TCGv_i32 tmp;
+ /*
+ * BLX <imm> would be useless on M-profile; the encoding space
+ * is used for other insns from v8.1M onward, and UNDEFs before that.
+ */
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
+ return false;
+ }
+
/* For A32, ARM_FEATURE_V5 is checked near the start of the uncond block.
*/
if (s->thumb && (a->imm & 2)) {
return false;
--
2.20.1
[PATCH 03/10] target/arm: Implement v8.1M conditional-select insns, Peter Maydell, 2020/10/12
[PATCH 09/10] target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension, Peter Maydell, 2020/10/12
[PATCH 05/10] target/arm: Don't allow BLX imm for M-profile,
Peter Maydell <=
[PATCH 08/10] target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile, Peter Maydell, 2020/10/12
[PATCH 04/10] target/arm: Make the t32 insn[25:23]=111 group non-overlapping, Peter Maydell, 2020/10/12
[PATCH 06/10] target/arm: Implement v8.1M branch-future insns (as NOPs), Peter Maydell, 2020/10/12
[PATCH 10/10] target/arm: Fix writing to FPSCR.FZ16 on M-profile, Peter Maydell, 2020/10/12