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Re: [Gnucap-devel] commands in spectre mode.

From: Dan McMahill
Subject: Re: [Gnucap-devel] commands in spectre mode.
Date: Fri, 30 Nov 2007 22:19:28 -0500
User-agent: Mail/News (X11/20070512)

al davis wrote:
Questions for spectre users ...

I am working in the finer points of multi-language support, trying to determine what to put in. It will be a subset for now.

"model" and "subckt" work. General elements work within "model" blocks with spectre format.

In spectre mode, the main circuit is in a main space, like spice. That will be done,

Commands are prefixed with an instance name. That can be done but isn't yet.

I am only looking at input now. Not doing anything about output matching yet.

Now the questions...

1. When a command is prefixed with an instance name, what to do with the name?

Spectre uses it to name the results files.  For example

tran1 tran start=0 stop=1u ....
tran2 tran start=1u stop=2u
mysim ac ....

will produce results files called "tran1.tran", "tran2.tran", "".

commands are in fact instances just like elements (except their order of appearance matters)

2. Are commands sequential, like normal gnucap commands, or like mixed batch of cards, like spice?

sequential but the whole topology of the circuit is read in first. i.e. you can put your analysis commands before the circuit netlist if you want.

3. How to set up probes?

you'll find stuff like this:

finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
saveOptions options save=allpub

These statements control things like what is written out and what signals are saved.

4. Are there order requirements? For example, is it necessary to have a "model" before its instance? Do commands need to be after the circuit is described?

commands may come before the circuit is described. It appears that it must read the whole netlist once to get the circuit and then goes throuh again to do the commands.

subcircuits can be instantiated before they are defined. I *think* the same is true for models.

5. Can you have model within subckt?  subckt within subckt?

yes, yes.  They have subckt scope then.

You can also put analysis instances in a subcircuit.  for example

// define the circuit

// define some sims we'd like to run
subckt mysims
ac1 ac start=1k stop=10e6 dec=25
tran1 tran start=0 stop=10u
ends mysims

// run the sims
mysims1 mysims

// modify some value
alter1 alter <rest of alter statement>

// rerun the sims
mysims2 mysims

This will give results files called mysims1.ac1, mysims1.tran1, mysims2.ac1, mysims2.tran1

6. What other questions should I be asking?

// define certain nodes to have global scope
global <list of nodes>

// list of parameters.  Can be at the "top" level or within a subckt
parameters <var1>=<default1> <var2>=<default2>

// include the entire contents of a file
// specte can do "~" expansion
include "/path/to/myfile"

// include a section from a file
include "/some/model/file" section=<mysection>

includes can be nested, i.e. an included file can include other files, it can even include other sections of itself. Included files act just like #include in C (i.e., it is like you pasted the contents in)

// include a verilog-A file
ahdl_include "/path/to/"

nets and instance names can be pretty nasty if you escape certain special characters.

top\|I1\|I2\|R1 (node1 node2) ....

you can escape [|():], don't need to escape [a-zA-Z0-9_]. I'm sure this list is not complete.

subcircuits (and probably the top level circuit) can have conditionals that affect the circuit topology:

subckt myckt a b
parameters p=0

if( p==0)
R1 (a b) resistor r=1k
L1 (a b) inductor l=1u
ends myckt

Lseries (in out) myckt p=0
Rshunt (out gnd) myckt p=1

you can use this notation too

value=(p==1 ? <val1> : <val2>)

I'm sure there must be more you care about.


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