[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Gnucap-devel] commands in verilog mode.
From: |
al davis |
Subject: |
[Gnucap-devel] commands in verilog mode. |
Date: |
Fri, 30 Nov 2007 19:13:39 -0500 |
User-agent: |
KMail/1.9.7 |
Verilog doesn't specify commands. As far as I know, there are
no existing native Verilog-AMS simulators. It looks like
gnucap is leading here.
From what I see,in commercial simulators, Verilog-AMS is only
supported through something like a plugin mechanism. The main
circuit seems to be spice format, or maybe a proprietary
format.
It looks to me that the "main" circuit, if it is done in
Verilog, is just a "module" that is not instantiated, and you
somehow say to use it, in a simulator dependent manner.
Probably the most common way is to instantiate it in Spice
format.
I am thinking of adding capability to have a main circuit, in
the main scope like commands, just a list in Verilog format,
and keep gnucap commands order dependent as they are. This is
easiest to do, and I think the best way.
Since the first argument on a Verilog "module instantiation" is
a type, the whole system is very consistent, and fits well with
interactive use.
.....
ground 0;
module vdiv(in, out, gnd);
resistor #(1k) r1 (in, out);
resistor #(1k) r2 (out, gnd);
endmodule
vdiv divider (1 2 0);
vsource #(.dc(5)) v1 (1 0);
probe .....
dc........
(plain gnucap commands, as they are)
If you want everything in modules, and one (call it "main"
starts it all, just instantiate "main" only ..
main m1;
There is even a way to do multiple simultaneous simulations ...
main m1;
main m2;
etc....
This works in other modes too.
Most jobs will be mixed languages. One in Spice, one in
Verilog-A, another in Spectre, .... That part is easy.
comments?
- [Gnucap-devel] commands in verilog mode.,
al davis <=