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[cfk]

I have been successful in manipulating the tool-SiliconCompiler-{vhdl} example to place sclib modules, route them and build a pad frame. I can see how to change to VHDL code and change the IC created a bit.

 

Now, I have a question relating to Verilog if I may. It turns out that I have a design in Verilog consisting of 50 or so source files. It snthesizes just fine and I can put it into an FPGA. I can compile it with Icarus Verilog and I can an output of the form:

 

SYM, <section_name>, INV, LIBVER=2.0.0

    PIN, O, O, <output_of_INV>

    PIN, I, I, <input_ to_ INV>

END

 

and of course, all of the rest of the gates in the design. So, the question is, how would I go about getting my Verilog code into Electric. I suppose one option is for me to write a program to manipulate the netlist output of Icarus Verilog so that the netlist format is acceptable to Electric so I can attempt to boot-strap my understanding to the next level.

 

Perhaps, there allready exists either a Verilog compiler that has an output compatible with Electrics input (please dont say Synopsis, Cadence, or Mentor Graphics as I dont have any sheckles for this project other then my weekend time). Or there is some translator that simplifies this issue.

 

Anyone have any suggestions or comments.

 

 

Charles Krinke
http://home.pacbell.net/cfk
address@hidden