EDIF

[cfk]

In an attempt to understand a bit about how to input a chip design into
Electric in EDIF, I created a small FPGA using the Xilinx ISE toolset with
basically a few inputs, outputs and a couple of flip flops. When I import
into Electric, I get top{ic} which looks like just a port list and top{sch}
which looks like a bunch of off page references. I get some facets called
buf, inv, ipad, opad and the like but I dont see any connectivity.

So, my question, based mostly on unfamiliarity with Electric, is how would I
go about getting a design in EDIF form from one toolset written in say
Verilog into Electric with connectivity and then tell Electric to create a
IC using the sclib and pads4u. Perhaps it is there just under the surface
waiting for me to get smart enough to click the correct button.

Charles