[Commit-gnuradio] r8528 - usrp2/trunk/fpga/top/u2_rev2

[matt]

Author: matt
Date: 2008-05-28 18:40:17 -0600 (Wed, 28 May 2008)
New Revision: 8528

Modified:
   usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ise
   usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj
Log:
these result in something that meets timing


Modified: usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ise
===================================================================
(Binary files differ)

Modified: usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj
===================================================================
--- usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj    2008-05-29 00:39:37 UTC (rev 
8527)
+++ usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj    2008-05-29 00:40:17 UTC (rev 
8528)
@@ -3,16 +3,23 @@
 verilog work "../../opencores/uart16550/rtl/verilog/raminfr.v"
 verilog work "../../control_lib/ram_2port.v"
 verilog work "../../control_lib/gray_send.v"
+verilog work "../../sdr_lib/sign_extend.v"
+verilog work "../../sdr_lib/round.v"
+verilog work "../../sdr_lib/add2_and_round.v"
+verilog work "../../sdr_lib/add2.v"
 verilog work "../../opencores/uart16550/rtl/verilog/uart_tfifo.v"
 verilog work "../../opencores/uart16550/rtl/verilog/uart_rfifo.v"
 verilog work "../../coregen/fifo_generator_v4_1.v"
 verilog work "../../control_lib/shortfifo.v"
 verilog work "../../control_lib/longfifo.v"
 verilog work "../../control_lib/fifo_2clock.v"
-verilog work "../../sdr_lib/sign_extend.v"
+verilog work "../../sdr_lib/round_reg.v"
 verilog work "../../sdr_lib/cordic_stage.v"
 verilog work "../../sdr_lib/cic_int_shifter.v"
 verilog work "../../sdr_lib/cic_dec_shifter.v"
+verilog work "../../sdr_lib/add2_reg.v"
+verilog work "../../sdr_lib/add2_and_round_reg.v"
+verilog work "../../sdr_lib/acc.v"
 verilog work "../../opencores/uart16550/rtl/verilog/uart_transmitter.v"
 verilog work "../../opencores/uart16550/rtl/verilog/uart_sync_flops.v"
 verilog work "../../opencores/uart16550/rtl/verilog/uart_receiver.v"
@@ -39,6 +46,7 @@
 verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v"
 verilog work "../../eth/rtl/verilog/MAC_rx/CRC_chk.v"
 verilog work "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v"
+verilog work "../../control_lib/srl.v"
 verilog work "../../control_lib/fifo_2clock_casc.v"
 verilog work "../../control_lib/CRC16_D16.v"
 verilog work "../../control_lib/cascadefifo2.v"
@@ -48,8 +56,12 @@
 verilog work "../../serdes/serdes_rx.v"
 verilog work "../../serdes/serdes_fc_tx.v"
 verilog work "../../serdes/serdes_fc_rx.v"
-verilog work "../../sdr_lib/round.v"
+verilog work "../../sdr_lib/small_hb_int.v"
+verilog work "../../sdr_lib/small_hb_dec.v"
+verilog work "../../sdr_lib/hb_interp.v"
+verilog work "../../sdr_lib/hb_dec.v"
 verilog work "../../sdr_lib/cordic.v"
+verilog work "../../sdr_lib/cic_strober.v"
 verilog work "../../sdr_lib/cic_interp.v"
 verilog work "../../sdr_lib/cic_decim.v"
 verilog work "../../opencores/uart16550/rtl/verilog/uart_wb.v"
@@ -68,7 +80,6 @@
 verilog work "../../eth/rtl/verilog/flow_ctrl_rx.v"
 verilog work "../../eth/rtl/verilog/eth_miim.v"
 verilog work "../../eth/rtl/verilog/Clk_ctrl.v"
-verilog work "../../control_lib/strobe_gen.v"
 verilog work "../../control_lib/setting_reg.v"
 verilog work "../../control_lib/mux8.v"
 verilog work "../../control_lib/mux4.v"