[Commit-gnuradio] r8529 - usrp2/trunk/fpga/sdr_lib

[matt]

Author: matt
Date: 2008-05-28 18:41:50 -0600 (Wed, 28 May 2008)
New Revision: 8529

Modified:
   usrp2/trunk/fpga/sdr_lib/cic_dec_shifter.v
   usrp2/trunk/fpga/sdr_lib/cic_decim.v
   usrp2/trunk/fpga/sdr_lib/cic_int_shifter.v
   usrp2/trunk/fpga/sdr_lib/cic_interp.v
Log:
fixes so that we don't need to send N-1


Modified: usrp2/trunk/fpga/sdr_lib/cic_dec_shifter.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/cic_dec_shifter.v  2008-05-29 00:40:17 UTC (rev 
8528)
+++ usrp2/trunk/fpga/sdr_lib/cic_dec_shifter.v  2008-05-29 00:41:50 UTC (rev 
8529)
@@ -21,13 +21,12 @@
 
 
 // NOTE   This only works for N=4, max decim rate of 128
-// NOTE   signal "rate" is ONE LESS THAN the actual rate
+// NOTE   signal "rate" is EQUAL TO the actual rate, no more -1 BS
 
-module cic_dec_shifter(clock,rate,signal_in,signal_out);
+module cic_dec_shifter(rate,signal_in,signal_out);
    parameter bw = 16;
    parameter maxbitgain = 28;
 
-   input     clock;
    input [7:0] rate;
    input       wire [bw+maxbitgain-1:0] signal_in;
    output      reg [bw-1:0] signal_out;
@@ -69,38 +68,38 @@
       endcase // case(rate)
    endfunction // bitgain
    
-   wire [4:0]    shift = bitgain(rate+1);
+   wire [4:0]    shift = bitgain(rate);
    
    // We should be able to do this, but can't ....
    // assign     signal_out = signal_in[shift+bw-1:shift];
    
-   always @(posedge clock)
+   always @*
      case(shift)
-       5'd0  : signal_out <= signal_in[0+bw-1:0];
-       5'd4  : signal_out <= signal_in[4+bw-1:4];
-       5'd7  : signal_out <= signal_in[7+bw-1:7];
-       5'd8  : signal_out <= signal_in[8+bw-1:8];
-       5'd10 : signal_out <= signal_in[10+bw-1:10];
-       5'd11 : signal_out <= signal_in[11+bw-1:11];
-       5'd12 : signal_out <= signal_in[12+bw-1:12];
-       5'd13 : signal_out <= signal_in[13+bw-1:13];
-       5'd14 : signal_out <= signal_in[14+bw-1:14];
-       5'd15 : signal_out <= signal_in[15+bw-1:15];
-       5'd16 : signal_out <= signal_in[16+bw-1:16];
-       5'd17 : signal_out <= signal_in[17+bw-1:17];
-       5'd18 : signal_out <= signal_in[18+bw-1:18];
-       5'd19 : signal_out <= signal_in[19+bw-1:19];
-       5'd20 : signal_out <= signal_in[20+bw-1:20];
-       5'd21 : signal_out <= signal_in[21+bw-1:21];
-       5'd22 : signal_out <= signal_in[22+bw-1:22];
-       5'd23 : signal_out <= signal_in[23+bw-1:23];
-       5'd24 : signal_out <= signal_in[24+bw-1:24];
-       5'd25 : signal_out <= signal_in[25+bw-1:25];
-       5'd26 : signal_out <= signal_in[26+bw-1:26];
-       5'd27 : signal_out <= signal_in[27+bw-1:27];
-       5'd28 : signal_out <= signal_in[28+bw-1:28];
+       5'd0  : signal_out = signal_in[0+bw-1:0];
+       5'd4  : signal_out = signal_in[4+bw-1:4];
+       5'd7  : signal_out = signal_in[7+bw-1:7];
+       5'd8  : signal_out = signal_in[8+bw-1:8];
+       5'd10 : signal_out = signal_in[10+bw-1:10];
+       5'd11 : signal_out = signal_in[11+bw-1:11];
+       5'd12 : signal_out = signal_in[12+bw-1:12];
+       5'd13 : signal_out = signal_in[13+bw-1:13];
+       5'd14 : signal_out = signal_in[14+bw-1:14];
+       5'd15 : signal_out = signal_in[15+bw-1:15];
+       5'd16 : signal_out = signal_in[16+bw-1:16];
+       5'd17 : signal_out = signal_in[17+bw-1:17];
+       5'd18 : signal_out = signal_in[18+bw-1:18];
+       5'd19 : signal_out = signal_in[19+bw-1:19];
+       5'd20 : signal_out = signal_in[20+bw-1:20];
+       5'd21 : signal_out = signal_in[21+bw-1:21];
+       5'd22 : signal_out = signal_in[22+bw-1:22];
+       5'd23 : signal_out = signal_in[23+bw-1:23];
+       5'd24 : signal_out = signal_in[24+bw-1:24];
+       5'd25 : signal_out = signal_in[25+bw-1:25];
+       5'd26 : signal_out = signal_in[26+bw-1:26];
+       5'd27 : signal_out = signal_in[27+bw-1:27];
+       5'd28 : signal_out = signal_in[28+bw-1:28];
        
-       default : signal_out <= signal_in[28+bw-1:28];
+       default : signal_out = signal_in[28+bw-1:28];
      endcase // case(shift)
 
 endmodule // cic_dec_shifter

Modified: usrp2/trunk/fpga/sdr_lib/cic_decim.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/cic_decim.v        2008-05-29 00:40:17 UTC (rev 
8528)
+++ usrp2/trunk/fpga/sdr_lib/cic_decim.v        2008-05-29 00:41:50 UTC (rev 
8529)
@@ -29,7 +29,7 @@
      input strobe_in,
      input strobe_out,
      input [bw-1:0] signal_in,
-     output [bw-1:0] signal_out);
+     output reg [bw-1:0] signal_out);
 
    localparam       maxbitgain = N * log2_of_max_rate;
    
@@ -77,9 +77,12 @@
            end
        end // if (enable && strobe_out)
    
-   wire [bw+maxbitgain-1:0] signal_out_unnorm = pipeline[N-1];
+   wire [bw-1:0] signal_out_unreg;
    
    cic_dec_shifter #(bw)
-     cic_dec_shifter(clock,rate,signal_out_unnorm,signal_out);
+     cic_dec_shifter(rate,pipeline[N-1],signal_out_unreg);
+
+   always @(posedge clock)
+     signal_out <= signal_out_unreg;
    
 endmodule // cic_decim

Modified: usrp2/trunk/fpga/sdr_lib/cic_int_shifter.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/cic_int_shifter.v  2008-05-29 00:40:17 UTC (rev 
8528)
+++ usrp2/trunk/fpga/sdr_lib/cic_int_shifter.v  2008-05-29 00:41:50 UTC (rev 
8529)
@@ -21,7 +21,7 @@
 
 
 // NOTE   This only works for N=4, max interp rate of 128
-// NOTE   signal "rate" is ONE LESS THAN the actual rate
+// NOTE   signal "rate" is EQUAL TO the actual rate (no more -1 BS)
 
 module cic_int_shifter(rate,signal_in,signal_out);
    parameter bw = 16;
@@ -35,6 +35,8 @@
       input [7:0] rate;
       case(rate)
        // Exact Cases
+       8'd1 : bitgain = 0;
+       8'd2 : bitgain = 3;
        8'd4 : bitgain = 6;
        8'd8 : bitgain = 9;
        8'd16 : bitgain = 12;
@@ -42,7 +44,8 @@
        8'd64 : bitgain = 18;
        8'd128 : bitgain = 21;
        
-       // Nearest without overflow
+       // Nearest without overflow     
+       8'd3 : bitgain = 5;
        8'd5 : bitgain = 7;
        8'd6 : bitgain = 8;
        8'd7 : bitgain = 9;
@@ -62,13 +65,15 @@
       endcase // case(rate)
    endfunction // bitgain
    
-   wire [4:0]    shift = bitgain(rate+1);
+   wire [4:0]    shift = bitgain(rate);
    
    // We should be able to do this, but can't ....
    // assign     signal_out = signal_in[shift+bw-1:shift];
    
    always @*
      case(shift)
+       5'd0  : signal_out = signal_in[0+bw-1:0];
+       5'd3  : signal_out = signal_in[3+bw-1:3];
        5'd6  : signal_out = signal_in[6+bw-1:6];
        5'd9  : signal_out = signal_in[9+bw-1:9];
        5'd12 : signal_out = signal_in[12+bw-1:12];
@@ -76,6 +81,7 @@
        5'd18 : signal_out = signal_in[18+bw-1:18];
        5'd21 : signal_out = signal_in[21+bw-1:21];
        
+       5'd5  : signal_out = signal_in[5+bw-1:5];
        5'd7  : signal_out = signal_in[7+bw-1:7];
        5'd8  : signal_out = signal_in[8+bw-1:8];
        5'd10 : signal_out = signal_in[10+bw-1:10];

Modified: usrp2/trunk/fpga/sdr_lib/cic_interp.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/cic_interp.v       2008-05-29 00:40:17 UTC (rev 
8528)
+++ usrp2/trunk/fpga/sdr_lib/cic_interp.v       2008-05-29 00:41:50 UTC (rev 
8529)
@@ -29,7 +29,7 @@
      input strobe_in,
      input strobe_out,
      input [bw-1:0] signal_in,
-     output [bw-1:0] signal_out);
+     output reg [bw-1:0] signal_out);
    
    integer          i;
    localparam       maxbitgain = (N-1)*log2_of_max_rate;
@@ -75,11 +75,13 @@
               pipeline[i] <= #1 pipeline[i-1] - differentiator[i];
            end
        end
-   
-   wire [bw+maxbitgain-1:0] signal_out_unnorm = integrator[N-1];
 
+   wire [bw-1:0] signal_out_unreg;
    cic_int_shifter #(bw)
-       cic_int_shifter(rate,signal_out_unnorm,signal_out);
+     cic_int_shifter(rate,integrator[N-1],signal_out_unreg);
    
+   always @(posedge clock)
+     signal_out <= signal_out_unreg;
+   
 endmodule // cic_interp